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Day One -
Tuesday
November 1 |
Session |
Company or University |
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7:00 am - 5:00 pm |
Registration Open All Day |
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8:00 am - 08:15 am |
Welcome, Opening Remarks, and Conference Updates. Farhad Mafie, President
and CEO |
Savant |
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8:15 am - 08:45 am |
Keynote Speech: New Realities Mandate Fundamental Changes in
Competitive Strategies. Derek Lidow, President and CEO |
iSuppli |
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8:45 am - 12:00 am |
CPUs & DSPs for SoC
Applications |
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Flexible Multimedia SOC Platform.
Dr. Thanh Tran, Senior Member Technical Staff. |
Texas Instruments |
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Media
processing for wireless SOC applications: reduce design risk with
configurable processor cores.
Steve Leibson, Technology Evangelist |
Tensilica |
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9:45 am - 10:00 am |
Morning
Coffee Break |
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The
Challenges of Designing a Pure-Software H.264 Solution, Eran Briman,
Technology Director |
CEVA-DSP |
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Low Power
Video for Mobile SoCs. Kevin Christensen, Director Business Development
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Elixent |
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SOC
Implementation Of Wireless Security Using NPU Platform, Tulin E. Mangir,
Ph.D Engr |
CSU Long
Beach |
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Are Highly
Parallel Embedded DSPs Capable of Meeting the Area, Power, and Performance
Capabilities of Current ASIC Solutions?
Dr.
Nader Bagherzadeh |
Morpho
Technologies |
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12:00 pm - 1:00 pm
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Lunch
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1:00 pm - 1:30 pm |
Keynote Speech:
Why Memory has Become
The Technological Catalyst for the Mobile
Era,
Jon Kang, Senior Vice
President of Technical Marketing at Samsung Semiconductor
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Samsung |
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1:30 pm - 4:15 pm |
Memory sub-system for System-on-Chip Designs
Track Chairman:
Dave Bursky
Editor-at-Large,
Electronic Design
Magazine |
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Who’s
got the right of way? Choosing the right process and IP for your NVM based
SOC products, Peter Lee, President & CEO
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Aplus Flash Technology |
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On-chip
or Off-Chip? Non-Volatile Memory trends, Jim Cooke, Principal Applications
Engineer |
Micron
Semiconductor |
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An
embedded non-volatile memory, using standard logic CMOS, for SoC Design.
Michael Fliesler, Vice President of Engineering, Kilopass Technology, Inc. |
Kilopass
Technology |
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3:00
pm - 3:15 pm |
Afternoon
Coffee Break |
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I need more memory: Do I trench or do I stack?
Leung, Wing-Yu is Executive Vice President, Engineering and
Chief Technical Officer and a board member. |
MoSys |
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Silicon Aware IP Embedded
Memory Strategy for 65nm and Below.
Ken Potts, Sr. Product Marketing Director
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Virage Logic |
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4:15 pm - 5:15 pm
Panel |
Panel: Memory sub-system for System-on-Chip Designs
Moderator: Dave Bursky,
Editor-at-Large, Electronic Design
Magazine
Panelists:
1.
Robert Payne,
Senior vice president and general manager of System Technology and
Architecture, Philips Semiconductor
2. R. Mark Gogolewski, CTO,
Denali Software
3.
Jason So, Director of Business
Development, Custom LSI Strategic Business, NEC Electronics America, Inc.
4.
Jauher Zaidi,
CEO of Palmchip.
5.
Yohji Watanabe, Embedded Memory
Design Dept.
SoC R&D Center, Toshiba Corp.
6. TBD.
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4:30 pm - 8:30 pm |
Conference Exhibit
& Reception Open
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Day Two - Wednesday
November 2 |
Session |
Company or University |
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7:00 am - 5:00 pm |
Registration Open |
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8:00 am - 8:15 am |
Welcome and Opening Remarks, Technology/Market Trends. Farhad Mafie,
President and CEO |
Savant |
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8:15 am - 8:45 am |
Keynote Speech:
Professor Tummala, pettit
chair professor in Microsystems packaging |
Georgia Institute of
Technology |
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8:45 am - 12:00 pm |
New
Trends and Approaches in ASIC and SoC
Design |
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Broadband
Wireless Everywhere. A Step Closer, Ray Abrishami, Senior Director of SoC
Engineering and Marketing |
Fujitsu
Microelectronics |
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Deep
Sub-Micron Compound Complexity - System Level Package Interconnect Co-Design
Methodology, Robert Madge, Director, Technology Marketing |
LSI Logic |
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9:45 am - 10:00 am |
Morning Coffee Break |
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New Trends in
ASIC/SoC Design, Ronnie Vasishta, CEO |
eASIC |
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Improving Design Simulation and Verification using FPGAs and
Structured ASICs, Paul Hollingworth, Senior Director, HardCopy Product Group |
Altera |
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RF & Analog Integration, Paul Kempf – Chief Technology &
Strategy Officer |
Jazz
Semiconductor |
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90nm, 65nm, and below: Time for a New Foundry Model, Walter
Ng, Senior Director, Platform Alliances |
Chartered
Semiconductor |
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12:00 pm - 1:00 pm |
Lunch |
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1:00 pm - 1:30 pm |
Keynote Speech: "The Era of Open SoCs: Growing a VC Ecosystem in a
Standard Semiconductor Platform".
Dr. Juan-Antonio Carballo,
Venture Strategy Executive |
IBM |
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1:30 pm - 4:30 pm |
EDA Tools and
Methodologies for 65nm and Beyond |
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New Challenges in Front-End Design for
Nanometer SoCs.
Steve Carlson,
Director |
Cadence Design Systems
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An
Era of Design For Cost, Adam Traidman, President |
Giga Scale Integration
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What’s Up? Growth Areas in the
Electronics Industry. John Gallagher, Senior Director ASIC Synthesis
Marketing |
Synplicity |
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3:00 pm - 3:15 pm |
Afternoon Coffee Break |
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New Trends in SoC Testing &
Verifications. Dr.
Tamara Papalias, Department of
Electrical Engineering
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San Jose State University |
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New Tools for Adopting
Nanometer Process Technology, Dr. Ramon Acosta - Vice President of
Engineering
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Nascentric |
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Facts, Myths, and Methods:
The Hows and Whys of IC Power Reduction, Richard
Gordon. |
T-Zero Engineering |
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4:45 pm - 5:30 pm
Panel |
Panel: Low
Power Design Challenges in Complex SoC & ASIC Designs
Moderator: Ron
Wilson, Editor, EE Times.
Panelists:
1. Sunil
Baliga, VP Marketing, K-Micro
2.
David Flynn, Engineering Fellow, ARM
3.
Steve Leibson, Technology Evangelist, Tensilica
4.
Susan
Runowicz-Smith.
Cadence--Silicon
Design Chain Initiative.
5. TBD -
Toshiba
6.
Wing-Yu
Leung, CTO, MoSys.
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