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The 14th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 October 19 & 20, 2016

University of California, Irvine (UCI) - Calit2

13th International SoC Conference In Pictures. . .


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3rd International System-on-Chip (SoC) Conference & exhibit

Conference Program Agenda*


Day One - Tuesday

November 1


Company or University

    7:00 am - 5:00  pm Registration Open All Day  
    8:00 am - 08:15 am Welcome, Opening Remarks, and Conference Updates. Farhad Mafie, President and CEO Savant
    8:15 am - 08:45 am Keynote Speech: New Realities Mandate Fundamental Changes in Competitive Strategies.  Derek Lidow, President and CEO iSuppli
    8:45 am - 12:00 am

CPUs & DSPs for SoC Applications


Flexible Multimedia SOC Platform. Dr. Thanh Tran, Senior Member Technical Staff.

Texas Instruments


Media processing for wireless SOC applications: reduce design risk with configurable processor cores. Steve Leibson, Technology Evangelist


    9:45 am - 10:00 am Morning Coffee Break  
    The Challenges of Designing a Pure-Software H.264 Solution, Eran Briman, Technology Director



Low Power Video for Mobile SoCs. Kevin Christensen, Director Business Development 

    SOC Implementation Of Wireless Security Using NPU Platform, Tulin E. Mangir, Ph.D Engr CSU Long Beach
    Are Highly Parallel Embedded DSPs Capable of Meeting the Area, Power, and Performance Capabilities of Current ASIC Solutions? Dr. Nader Bagherzadeh Morpho Technologies
    12:00 pm - 1:00 pm



  1:00 pm - 1:30 pm

Keynote Speech: Why Memory has Become The Technological Catalyst for the Mobile Era, Jon Kang, Senior Vice President of Technical Marketing at Samsung Semiconductor

    1:30 pm - 4:15 pm

Memory sub-system for System-on-Chip Designs

Track Chairman: Dave Bursky

Editor-at-Large, Electronic Design Magazine 


Who’s got the right of way? Choosing the right process and IP for your NVM based SOC products, Peter Lee, President & CEO

Aplus Flash Technology


On-chip or Off-Chip? Non-Volatile Memory trends, Jim Cooke, Principal Applications Engineer

Micron Semiconductor


An embedded non-volatile memory, using standard logic CMOS, for SoC Design. Michael Fliesler, Vice President of Engineering, Kilopass Technology, Inc.

Kilopass Technology

    3:00 pm - 3:15 pm Afternoon Coffee Break  

I need more memory: Do I trench or do I stack? Leung, Wing-Yu is Executive Vice President, Engineering and Chief Technical Officer and a board member.



Silicon Aware IP Embedded Memory Strategy for 65nm and Below. Ken Potts, Sr. Product Marketing Director

Virage Logic


  4:15 pm - 5:15 pm


Panel: Memory sub-system for System-on-Chip Designs  

Moderator: Dave Bursky, Editor-at-Large, Electronic Design Magazine


1. Robert Payne,  Senior vice president and general manager of System Technology and Architecture, Philips Semiconductor

2. R. Mark Gogolewski, CTO, Denali Software

3. Jason So, Director of Business Development, Custom LSI Strategic Business, NEC Electronics America, Inc.

4. Jauher Zaidi, CEO of Palmchip.

5. Yohji Watanabe, Embedded Memory Design Dept.
SoC R&D Center, Toshiba Corp.

6. TBD.



4:30 pm - 8:30 pm

Conference Exhibit & Reception Open


Day Two - Wednesday

November 2


Company or University

    7:00 am - 5:00  pm Registration Open  
    8:00 am - 8:15 am Welcome and Opening Remarks, Technology/Market Trends. Farhad Mafie, President and CEO Savant
    8:15 am - 8:45 am Keynote Speech: Professor Tummala, pettit chair professor in Microsystems packaging Georgia Institute of Technology
    8:45 am - 12:00 pm

New Trends and Approaches in ASIC and SoC Design


Broadband Wireless Everywhere. A Step Closer, Ray Abrishami, Senior Director of SoC Engineering and Marketing

Fujitsu Microelectronics

Deep Sub-Micron Compound Complexity - System Level Package Interconnect Co-Design Methodology, Robert Madge, Director, Technology Marketing

LSI Logic

  9:45 am - 10:00 am

Morning Coffee Break  
    New Trends in ASIC/SoC Design, Ronnie Vasishta, CEO eASIC

Improving Design Simulation and Verification using FPGAs and Structured ASICs, Paul Hollingworth, Senior Director, HardCopy Product Group


RF & Analog Integration, Paul Kempf – Chief Technology & Strategy Officer

Jazz Semiconductor

90nm, 65nm, and below: Time for a New Foundry Model, Walter Ng, Senior Director, Platform Alliances

Chartered Semiconductor
    12:00 pm - 1:00 pm Lunch  
    1:00 pm - 1:30 pm

Keynote Speech: "The Era of Open SoCs: Growing a VC Ecosystem in a Standard Semiconductor Platform".
Dr. Juan-Antonio Carballo,
Venture Strategy Executive

    1:30 pm - 4:30 pm

EDA Tools and Methodologies for 65nm and Beyond

    New Challenges in Front-End Design for Nanometer SoCs. Steve Carlson, Director Cadence Design Systems
    An Era of Design For Cost, Adam Traidman, President Giga Scale Integration
    What’s Up? Growth Areas in the Electronics Industry. John Gallagher, Senior Director ASIC Synthesis Marketing Synplicity
    3:00 pm - 3:15 pm Afternoon Coffee Break  

New Trends in SoC Testing & Verifications. Dr. Tamara Papalias, Department of Electrical Engineering

San Jose State University

New Tools for Adopting Nanometer Process Technology, Dr. Ramon Acosta - Vice President of Engineering

    Facts, Myths, and Methods: The Hows and Whys of IC Power Reduction, Richard Gordon. T-Zero Engineering
    4:45 pm - 5:30 pm


Panel: Low Power Design Challenges in Complex SoC & ASIC Designs

Moderator: Ron Wilson, Editor, EE Times.



1. Sunil Baliga, VP Marketing, K-Micro

2. David Flynn, Engineering Fellow, ARM

3. Steve Leibson, Technology Evangelist, Tensilica

4. Susan Runowicz-Smith. Cadence--Silicon Design Chain Initiative.

5. TBD - Toshiba

6. Wing-Yu Leung, CTO, MoSys.



*Program is subject to change.  Savant Company Inc. reserves the right to revise or modify the above program at its sole discretion.

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Selected Participating Universities, Companies, and Media Sponsors

(a Partial List)


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Copyright © 2005 by Savant Company Inc. All rights reserved. 






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