ENGINEERING STUDENTS. . .
Lattice Semiconductor and IEEE
OC Solid-State Circuits Society (SSCS) cordially invites you to participate
in the 2018 SoC Student Design Contest (SoC-SDC) that will be held as part
of the 16th International System-on-Chip (SoC) Conference on Wednesday,
October 17, at UCI Calit2.
The SoC-SDC provides an
outstanding forum in which graduate and undergraduate students’ efforts can
be shared with an audience of academic and industrial technical experts. The
contest promotes excellence in the engineering- and computer science-related
designs within an academic environment and provides a forum in which
undergraduate/graduate engineering and computer science students’ ingenuity
can be shared with an audience of academic/industrial technical experts.
The participating students
will present their designs through posters at the 16th International SoC
Conference. Individuals or small teams with accepted abstracts will be
offered the chance to participate. Accepted abstracts will be published in
the conference proceedings and students will get the opportunity to present
a peer-proffered poster (and demo if available) as part of the presentation
SoC-SDC PROJECT PROPOSAL*
The SoC Student Design Contest
is designed to encourage engineering and computer science undergraduates and
graduate students to work on an original project based on Lattice
Semiconductor FPGA solutions and present their work at the 16th
International System-on-Chip (SoC) Conference Exhibit to a group of judges
from industry and academia. Interested students could complete their FPGA
design work either on a Lattice FPGA board or simply present a paper design
that list their design-related code.
Each project will be judged
based on its overall complexity, originality, and completion of the work.
Substantially extending sample projects with an extra spark of creativity
would be considered as an original design.
Neural network, sensor/signal
processing, machine vision, RISC-V (or other processors), sound processing,
real time DSP, audio processing / voice recognition, security applications,
software defined radio, bit-stream encode/decode, precise timing control,
autonomous (model) vehicles, programmable logic control, automation, robotic
control, Internet of Things (IoT), are just some of the exciting topics that
students can explore with their project designs.
“WILD & CRAZY” DESIGN PROJECTS
WE LOOK FORWARD TO HEARING
Don’t Miss Out!
THIS IS AN EXCELLENT
OPPORTUNITY TO GET PUBLISHED AND PRESENT AT AN INTERNATIONAL CONFERENCE IN
YOUR OWN BACK YARD!
October 5, 2018
(Extended to Friday, Oct
To participate in this contest, please submit your
proposed project abstract in MS Word (maximum 500 words) by providing a
high-level overview of the project. Abstract must include full name and
email addresses of all the participating students for each project (group
projects are encouraged). All abstracts must be submitted to:
Project Demonstration and Poster Presentation: Wednesday, October 17, 2018
All participating students
must present their project via a poster presentation on Wed, Oct 17, at 10
am (at UCI Calit2 building).
Posters must be displayed and
available for everyone to see on Wed, Oct 17, by 10 am.
Students that have completed
their Lattice FPGA project on a lattice development board must demonstrate
their board solution work to the judges. Students that have completed their
paper design, must provide all the design-related documentation during their
poster presentation for the Judges review.
Wednesday, October 17, 2018:
Projects will be reviewed and winners will be announced at the 16th
International SoC Conference Exhibit reception starting at 6:00 PM, at the
* First Prize: $650.00
* Second Prize: $250.00
* Third Prize: $100.00
(2) All participating
students (who have submitted their abstract and planning to present their
poster presentation on Wed, Oct 17) will receive a "2-Day Conference
(3) Names and pictures
of the winners will be displayed on the SoC Conference website. Abstracts of
contest participants will be published in the conference proceedings.
(1) Final Report format
must be in MS Word or PowerPoint.
(2) Poster size: 24x36
(or slightly larger).
(3) Poster presentation
date: Wed, Oct 17.
(4) Students must be at
the SoC Conference Exhibit area (Calit2 building) for poster setup & to
discuss their projects with the judges at 10 am on Wed, Oct 17
(5) Check the website
Note: Many types of
lattice demos boards are available for the low cost iCE40 line of FPGAs. This
includes the sub $10 Gnarly Grey UPDuino Board as well as other demo boards
from Lattice providing machine vision, sensor processing, and interface
capabilities. Please consider the following video for information about
common applications for this Low Cost FPGA
* SDC Program is subject to
change. Lattice Semiconductor, IEEE OC SSCS, UCI Calit2, Savant Company
Inc. and the SoC Conference Organizing Committee reserve the right to revise
or modify the above program at its sole discretion. Please visit the SoC
Conference website regularly for the latest updates and changes.
For questions regarding the Student Design
Contest, please contact:
Click Here To
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Parking for Calit2 Building at the University of California, Irvine (UCI)