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Workshop # 1 |
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FPGA Transceivers at 8.5 Gbps and Beyond at 40nm Process Technology.
By
Mike Li, Ph.D., Principle Architecture & Distinguished Engineer, Altera
Corporation
This workshop will focus on leading-edge FPGA transceiver technology at 8.5 Gbps and beyond at the 40 nm process technology node on Altera’s new Stratix
IV GX FPGA. We will examine the performance and capabilities of the device,
as well as discuss specific target applications, review the market trends
and examine the requirements of this technology and applications requiring
multiple Gbps high-speed transceivers. A discussion of the innovative
technologies implemented in the Stratix IV FPGA that meet and often exceed
the performance and power requirements set by the industry’s technology
roadmap and/or standards.
Novel and cutting-edge technologies for
equalization (adaptive linear, DFE), clock and data recovery (hybrid CDR),
ultra low-jitter clock generation (ring and LC based oscillators), and
low-power design will be covered. Performance advancements in terms of
jitter output, jitter tolerance, signal and power integrity will also be
presented in detail.
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Date,
Time & Location |
Wednesday, November 5th from 2:00 PM – 4:45 PM in Room A.
Radisson Hotel Newport Beach. |
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Register
for this Workshop
Early Bird Price is only $49! |
To
register for this Workshop, click here:
Altera Workshop Registration |
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Workshop # 2 |
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JRI Technology |
Digital TV on a Chip – An Overview
By
Dr. Jordan Isailovic, President, JRI Technology. Savant Affiliate.
DTV’s rapid growth in popularity is spurred by the high-definition video
quality as well as the availability of a variety of new features and
services including video on demand (VoD), gaming, security, PVR, interactive
TV, merchandising and Web browser capabilities. In this half-day Workshop,
an overview of Digital TV technology and its system-level block diagram will
be provided and main blocks will be discussed. Dr. Jordan Isailovic, will
covers the video chain from the initial capture of video content to the
final viewing experience. Applicable compression technologies such as MPEG
will be reviewed. Topics that will be reviewed, include:
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Digital Television architecture and functionality
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MPEG TV
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System Interfaces
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Major video processing building blocks
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Strategic consideration for the design of digital TV system-on-chip
Trade-off between performance and cost.
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Multi-format picture decoding in support of high definition AVC, H.264,
VC-1, AVS and MPEG-2 streams.
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Aspect ratio conversions; AFD, closed captions 608/708
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Synchronization in the MPEG world; Lip-sync and latency issues
Conditional access, authorization and control
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Major trends and Future A/V Standards, H.265, etc.
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Looking beyond HD: 3D, Hi-vision, mobile TV, etc.
Who Should Attend:
Engineers, technical management, system architects, technology analysts,
systems developers and integrators, etc., who are interested in getting a
comprehensive overview of the Digital TV technology and its single chip
opportunity would greatly benefit from this half-day informative workshop.
Instructor: Dr. Jordan Isailovic is a Professor of Electrical
Engineering at California State University. He is the author of Videodisc
and Optical Memory Technologies and Videodisc Systems: Theory and
Applications. He has authored numerous technical articles and holds several
patents on digital information storage techniques and video signal
processing. He presented the world's first public engineering course on
videodisc technology (January 1982) and taught the world's first graduate
courses on videodisc and optical memories (CD, CD-ROM, etc.). For more
details about Dr. Isailovic see:
www.jritechnology.com/Instructor.pdf. |
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Date, Time & Location |
Please let us know if you are interested in this Workshop:
SoC@SavantCompany.com
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Register
for this Workshop
Early Bird Price is only $49! |
Please let us know if you are interested in this Workshop:
SoC@SavantCompany.com
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Workshop # 3 |
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Understanding and Effectively Suppressing the Noise Coupling in Mixed-Signal
SoC Applications. By:
Dr. Cosmin Iorga.
The understanding of noise coupling phenomena is essential to semiconductor
design engineers who must deal with the challenges of integrating more and
more functionality on a single chip. This tutorial provides a practical
approach to the analysis of noise coupling mechanisms at device, chip
substrate, package, and PCB levels, the implementation of efficient
suppression techniques, and the simulation of noise coupling in various
stages of the design flow. I addition to conventional suppression and
simulation techniques, circuit level noise cancellation methodologies and
practical procedures for modeling the noise coupling early in the
architectural stages of the design are also presented.
For workshop description,
please visit:
Noise Coupling
Instructor: Dr. Cosmin Iorga has earned his Ph.D. in Electrical
Engineering form Stanford University. His research work and dissertation
focused on the analysis, modeling, and suppression of noise coupling in
integrated circuits. Dr. Cosmin Iorga has accumulated more than 15 years of
experience in high-speed circuit design and troubleshooting at system,
board, and integrated circuit levels, with emphasis on signal integrity and
noise coupling reduction. Dr. Cosmin Iorga has filed more than 10 patents
with 6 granted so far, covering innovative solutions in noise coupling
reduction and signal integrity. Dr. Cosmin Iorga is the author of the book
"Noise Coupling in Integrated Circuits: A Practical Approach to Analysis,
Modeling, and Suppression". Dr. Cosmin Iorga is founder and president of
NoiseCoupling.com, a company that focuses on research of noise coupling in
mixed-signal integrated circuits and systems-on-chip, and noise coupling
education through technical seminars and hands-on workshops.
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Date, Time & Location
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Please let us know if you are interested in this Workshop:
SoC@SavantCompany.com
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Register
for this Workshop |
Please let us know if you are interested in this Workshop:
SoC@SavantCompany.com
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Workshop # 4 |
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Innovative Memory Complier for 1T, 6T, 8T, OTP, MTP, NVM, CAM, Etc.
By
Cyrus Afghahi, Ph.D., CEO, Novelics
This workshop will focus on Embedded Memory architecture, design, and
development by using an innovative memory complier. Participants will be
able to see how to design complex embedded memory IPs using a web-based
complier in a few seconds!
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Date, Time & Location
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Please let us know if you are interested in this Workshop:
SoC@SavantCompany.com
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Register
for this Workshop |
Please let us know if you are interested in this Workshop:
SoC@SavantCompany.com
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Workshop # 5 |
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Innovative Business Approaches in Chip Design, Hardware Design, Software
development, etc.
By
Jauher Zaidi,
President & CEO, PalmChip
TBD
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Date, Time & Location |
Please let us know if you are interested in this Workshop:
SoC@SavantCompany.com
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Register
for this Workshop |
Please let us know if you are interested in this Workshop:
SoC@SavantCompany.com
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Program Summary
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SoC Conference Day 1 |
Wednesday, November 5, 2008 |
8:00 am - 6:30 pm |
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SoC Conference Day 2 |
Thursday, November 6, 2008 |
8:00 am - 6:30 pm |
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SoC Table-Top Exhibit |
Wednesday, November 5, 2008 |
4:30 pm - 9:00 pm |
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SoC Workshops |
Check the Individual
Workshop Schedules |
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