6th International SoC Conference - Savant Company Inc.

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6th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

November 5 & 6, 2008 — Radisson Hotel Newport Beach, Southern California

Several Opportunities to Win an iPod shuffle, Technical Books & Many Unique Gifts Throughout the Conference Program . . .
Don't Miss Out!

The Most Informative, Targeted, and Affordably Priced

SoC, ASIC, ASSP, FPGA, and Foundry Technology Conference & Exhibit Event of the Year!

Conference Program Abstracts & Bios*


	8:00 - 8:15 Savant Company Inc.	Farhad Mafie, President and CEO of Savant Company Inc. "Welcome and Opening Remarks, Technology/Market Trends." Farhad has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. Farhad is the former Vice President of Marketing/Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing the entire Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth, Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.). He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer products & solutions based on ASSP and SoC Models. Farhad established Toshiba's on-line Tech-Support System as well as Toshiba's on-line System Solution Selling methodologies for all Toshiba's products in the North American markets. These on-line systems were adopted by Toshiba on a worldwide basis. He also developed Toshiba's ASSP Business Unit and Technical Sales Engineering Team as two brand new organizations for the company. Farhad has also worked at Lucent Technologies on marketing communications ICs, Toshiba Information Systems on product definition for Toshiba's notebooks and handheld products, Unisys on designing new processors and computer systems, and MSI Data on designing data collection products. He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. His combined business and academic experience has given Farhad a unique ability to effectively communicate complex new technologies to business professionals at all levels, as well as the ability to foresee emerging leading-edge technologies. Farhad is an author and a translator, and he writes articles for a variety of journals and Web-based magazines on technology and political affairs.
	8:15 am - 12:00 am	New Trends, Technologies, Methodologies, and Products for Your Next Chip Design Track Chairman: Farhad Mafie.
	8:15 - 8:45 Austria Microsystems AG	Philip Cacharelis, Engineering Director - Full Service Foundry SBU. Austria Microsystems AG. "SOC - Technology Perspective, Evolution and Challenges." Abstract: From the perspective of the process technologist, a SOC design is a circuit which merges the diverse functionality of multiple chips found, perhaps on a single PCB, into a single product. The PCB might be considered “the system”, hence the product would represent a “system on a chip”. Integrating a digital core (DSP or micro-processor) with precision analog circuits, program code and data storage as well as power handling/management elements can represent such an SOC design. This is often accomplished on silicon through the use of advanced Smart Power or BCD (Bipolar-CMOS-DMOS) technology which allows the integration of CMOS, Bipolar, and power devices as well as non-volatile memory and integrated passives such as capacitors and inductors. These technologies have been published extensively at various conferences and within technical journals and are most often used in the design of Automotive products. While the potential of these technologies and the sited product benefits of reduced cost, size, weight and improved reliability have been highlighted, the actual product usage of these technologies involves many circuit and device trade-offs and strong commercial considerations. Other factors in the potential productization of highly integrated technology are increasing digital content, ever-higher memory density requirements and the consideration between distributed and centralized intelligence in the applicable systems. Bio: Philip Cacharelis has over 20 years experience in a wide range of process technology development areas including CMOS, BiCMOS, embedded non-volatile memory, Smart Power and LCOS microdisplay technology. Currently, he is the Director of Engineering for the Full Service Foundry Business Unit of austriamicrosystems. In this role, he is responsible for the engineering activities within the business unit as well as for the development of corporate ESD/EMC solutions. Prior to this, he served as Technology Manager for Smart Power and Non-volatile Memory Technology at AMI Semiconductor. Here he directed three groups in the technology development of BCD, Embedded Non-volatile Memory and Advanced Device technologies. He was employed by National Semiconductor Corp. (Santa Clara, Ca.) for 14 years in technical management positions for the development of Smart Power and embedded non-volatile memory technology. While at National, he also lead a team in the development of a novel liquid-crystal-on-silicon (LCOS) microdisplay technology used in rear projection televisions systems. His interest in SOC stems from the multi-function circuit design capabilities enabled by so-called fully-loaded, up-integrated Smart Power technologies. He received a Bachelor of Science degree in Electrical Engineering from the University of Illinois, has published 16 technical articles and holds 10 patents.
	8:45 - 9:15 Silicon & Software Systems (S3)	Mark Barry, Technology Innovation Manager, Silicon & Software Systems (S3). "Advanced Power Management Techniques." Abstract: Green products and government directives are the key driving forces behind the development of power-aware designs across the board, from portable battery power devices to mains powered applications. Advanced power management techniques such as voltage islands and voltage gating can reduce power consumption but present significant challenges to the designer in terms of design methodologies and voltage regulation to the IC. This presentation will discuss the impact of advanced power management on aspects of the design flow such as architecture, verification and physical design and will include references to case studies showing how to avoid the common pitfalls. The talk will also analyze the challenges involved in integrating voltage regulators into deep-submicron SoCs in order to provide the lowest overall bill-of-materials cost for consumer applications. Bio: Mr. Mark Barry, Technology Innovation Manager, Silicon & Software Systems (S3). Speaker Bio: Mr. Barry joined S3 in 2003 and is responsible for the incubation of new silicon product and services ideas within the business and the management of S3’s Mixed-Signal Power Management IP Portfolio. Prior to S3 he was the Principal Architect with Bell Labs Wireless Advanced Technology Group and a Department Head with NewLogic Technologies. He is a senior member of the IEEE and has served on the steering and review committee of several conferences such as ISCAS. He is principal inventor of 4 US patents and represents S3 on the Irish Microelectronic Industry Design Association.
	9:15 - 9:45 iSuppli	Jordan Selburn, Principal Analyst, Core Silicon, iSuppli Corp Bio: Jordan came to iSuppli with decades of extensive experience in ASIC, programmable logic and semiconductor intellectual property (IP) analysis, product marketing, and engineering development. Prior to joining iSuppli, Jordan served as the Director of Product Marketing for Amphion Semiconductor, where he was tasked with managing the technical product marketing team. He launched products in all of Amphion’s product families in addition to providing in-depth sales support for the products and the IP business model. Prior to his tenure with Amphion, Jordan was the Principal Analyst for ASIC and IP at Gartner Group/Dataquest and as such was responsible for the evaluation and analysis of semiconductor IP as well as the ASIC and programmable logic markets. He formulated and presented tracking and forecasting on technology and market trends with particular emphasis on system-level integration as part of his duties at Gartner Group/Dataquest. Marketing Manager and Product Line Manager positions at LSI Logic preceded his employment at Gartner Group/Dataquest. At LSI Logic, Jordan was charged with establishing product positioning and pricing for their production ASIC products. In addition, he generated technical requirements and provided marketing direction to product development teams along with creating business plans for 0.6 micron and 0.35 micron technologies. Before LSI Logic, Jordan was an ASIC Technology Manager and a Corporate Applications Engineer at Valid Logic Systems/Cadence Design Systems and was also associated with Agilent/EEsof, Inc., and Harris Corporation in various engineering capacities. Jordan holds a Master of Science in Engineering Economic Systems from Stanford University in addition to an MBA with distinction from Santa Clara University and a BSEE with honors from the University of Michigan.
	9:45 - 10:00 Morning Break	Morning Break
	10:0- 10:30 Keynote University of Pennsylvania	Dr. Nader Engheta, H. Nedwill Ramsey Professor of Electrical and Systems Engineering, and Professor of Bioengineering. University of Pennsylvania "Circuits with Light at the Nanoscale." Abstract: Imagine circuit elements so small that you could fit many of them in a cell! What could you do with such optical nanocircuits? Would you be able to use them in wireless gadgets at nanoscales, like a “nanoradio”, that may connect our nanoworlds? Could these tiny optical nanocircuits be coupled with biological entities? The fields of metamaterials and plasmonic optics may provide road maps for such futuristic nanocircuits and wireless nanosystems. We have been developing and investigating some of the fundamental concepts and key features of metaplasmonic structures, devices, and circuits. These components may be envisioned as a tapestry of nanostructures of sizes much smaller than the wavelengths of light. This field, for which we have coined the term metactronics, addresses metamaterial-inspired optical nanocircuits and systems (N. Engheta, Science, 317, 1698-1702, 2007). . In my group, a variety of ideas for nanocircuit functions, optical antennas for beam shaping and photonic wireless at the nanoscale, optical nanoscopy, nanospectrometer for molecular spectroscopy, cloaking of particles, nanotagging and barcodes based on these optical circuits are being studied. In this talk, I will give an overview of these studies, present insights into these findings, and forecast future ideas and road maps in these areas. Bio: Nader Engheta is the H. Nedwill Ramsey Professor of Electrical and Systems Engineering, and Professor of Bioengineering, at the University of Pennsylvania. He received his B.S. degree in EE from the University of Tehran, and his M.S and Ph.D. degrees in EE from Caltech. Selected as one of the Scientific American Magazine 50 Leaders in Science and Technology in 2006 for developing the concept of optical lumped nanocircuits, he is a Guggenheim Fellow, an IEEE Third Millennium Medalist, IEEE Fellow, Optical Society of America Fellow, and the recipient of the 2008 George H. Heilmeier Award for Excellence in Research from UPenn, the Fulbright Naples Chair Award, NSF Presidential Young Investigator award, the UPS Foundation Distinguished Educator term Chair, and several teaching awards including the Christian F. and Mary R. Lindback Foundation Award and S. Reid Warren, Jr. Award. His current research activities span a broad range of areas including metamaterials and plasmonics, nanooptics and nanophotonics, biologically-inspired sensing and imaging, miniaturized antennas and nanoantennas, physics and reverse-engineering of polarization vision in nature, mathematics of fractional operators, and physics of fields and waves phenomena. He has given numerous keynote, invited, and plenary talks on these topics. He has co-edited the book entitled “Metamaterials: Physics and Engineering Explorations” by Wiley-IEEE Press, 2006.
	10:30- 11:00 Altera	Dr. Mojy Chian, Vice President of Technology Development Altera Corporation "FPGAs at the 40nm process node and beyond." Abstract: As semiconductor process geometries advance to 45-nanometer and below, we face significant development challenges both from a technical and business perspective. Factors such as power efficiency and cost of development have increased in significance with each new process generation and are now dominant concerns for design teams. When the required R&D costs for each new process generation are at least 50% higher (i.e. mask costs at 45-nm are over $3M), the focus must be on first silicon to production. To keep development costs down, solving these technical issues can be overcome by using the “comprehend, model and predict” methodology. This in turn will accomplish the goal of realizing a return on R&D investment, meeting time to market requirements, and future-proofing devices, which allows changes to be made later. This forces an ever-increasing number of applications to migrate to from ASIC to FPGA-based designs. Additionally, experiences with 45-nm design shows how techniques such as expanded statistical simulation and methodical testing in silicon throughout the design process are helping developers achieve first-time success in their designs. From a technical perspective new design approaches and techniques are needed to address these design challenges. These key technical challenges include lower voltage headroom, increased process variability, leakage control, ESD, strain induced proximity effect, temperature inversion, and speed to power conversion. How these challenges are being addressed is the key. By closely collaborating with a foundry partner design/process challenges, significant value can be extracted from advanced process technologies. These challenges include sophisticated device modeling that consider all deep sub-micron and proximity effects, statistical simulation and modeling tools to isolate and predict local and global variability, controlling leakage through multiple gate oxide transistors, selective Vt adjustments, and selective channel length adjustments. Bio: Mojy Chian is vice president of technology development at Altera Corporation. Before joining Altera, he was senior vice president of high-performance analog engineering at Mindspeed Technologies. While there, he was responsible for all aspects of IC product development, as well as leading the core technology group from 2000 to 2004. Prior to this, he was vice president of design automation and IP infrastructure for Conexant Systems, worked at Rockwell Semiconductor Systems, and spent ten years at Harris Semiconductor (later Intersil), leaving as the director of design systems. Mr. Chian received his BS, MS, and PhD in Electrical Engineering as well as an MS in Applied Math from Florida Tech. He holds two US patents, has authored or co-authored over 30 technical publications, and has served as adjunct professor at Florida Tech.
	11:00 - 11:30 Mentor Graphics	Glenn Perry, General Manager - Mentor Graphics ESL and Design Creation Division. "A ROI Model for Electronic System Level (ESL) Methodology." Abstract: Electronic System Level (ESL) design has enjoyed a history of success in the area of system analysis and virtual prototyping by SoC architects and software developers who needed early access to hardware. While this resulted in significant design optimization and shorter time-to-market benefits, the investment costs--primarily modeling--are significant and provide limited value to the existing register transfer level (RTL) design community, who struggle to implent and verify their latest designs. Today, models are the currency that dictate ROI on this revolutionary ESL methodology. However, these models, written at a level of abstraction above RTL, are scarce and creating them is not trivial. A collaborative approach to models and ESL methodology need to be deployed to reduce overall costs and design efficiencies. This 30-minute keynote, ideal for engineering management and their staff, will outline key strategies and available technologies, including synthesis and verification, that will enable the design community to drastically improve the ROI for an ESL design methodology. Bio: Glenn Perry has served as the General Manager of the ESL-HDL Design Business Unit at Mentor Graphics since 2004. He joined Mentor in 1999 as the engineering director for system level simulation tools, bringing over 20 years of experience in the electronics industry, focused in the simulation and analysis of Systems and IC Design. Prior to Mentor, Perry held engineering and management positions at Analogy(now Synopsis), Harris Semiconductor, Sandia National Laboratories and the United States Air Force Weapons Laboratory. Perry studied electrical engineering in the USAF and University of New Mexico.
	11:30 - 12:00 Jazz Semiconductor	Dr. Samir Chaudhry, Manager - Modeling & Characterization, Jazz Semiconductor. "Process Technology Platforms for Analog Intensive Mixed-Signal (AIMS) SoCs." Abstract: From an AIMS foundry perspective, a dedicated understanding of evolving customer needs is an important factor in determining process technology and design enablement roadmaps. Emerging requirements for process technology platforms to enable low-cost, fast time-to-market, and feature rich AIMS SOCs are discussed. On the technology side low-cost, high-performance and modular offerings are critical in enabling successful SOCs. With a goal of reducing time-to-market and prototyping costs, best-in-class design automation tools are imperative. Design enablement tools, including silicon verified device models and flexible design environments, allow customers to test, modify and improve the functionality and yield of new products on the computer long before the first prototype is manufactured. Trade-offs between SOCs and SIPs (Systems In a Package) are discussed within the context of AIMS systems. Bio: Dr. Samir Chaudhry leads the modeling activities for Jazz Semiconductor. His research interests include RF CMOS and statistical modeling. He is intimately associated with the Compact Modeling Council in developing industry standard compact models for circuit simulation. Prior to joining Jazz Semiconductor, he was a Distinguished Member of Technical Staff with Bell Labs, where he worked on Technology CAD and device modeling for scaled silicon technologies. Dr. Chaudhry received his PhD in Electrical Engineering from University of Florida. He has authored over 20 publications in peer-reviewed journals and conferences and has 14 patents in the field of silicon technology.
	11:30 - 12:00 Lunch	Lunch
		Hardware and Software Challenges for Multicore SoCs in Leading-Edge Applications Track Chairman: TBD.
	Panel	Panel: ““Hardware and Software Challenges for Multicore SoCs in Leading-Edge Applications”
	1:00 - 2:00 EDN Tensilica eSilicon Texas Instruments AMD Mentor Graphics LogicVision	Robert Cravotta, Technical Editor, Microprocessors, DSPs, Software, and Tools, EDN Worldwide. Moderator Bio: Robert Cravotta currently covers embedded processors, such as microprocessors, microcontrollers, and DSPs, as well as related tools for EDN's audience, providing the latest in technical insight, product updates, and architectural discussions in this vital industry area. Prior to EDN, he work at Boeing and Rockwell where he worked on the control systems for a range of projects including autonomous vehicles and power management for aircraft and the space station. In addition to a BSCSE from UCLA's School of Engineering and Applied Science, Robert has a MS in Engineering Management from California State University (Northridge). 1: Steve Leibson, Technology Evangelist. 2: Jack Harding, Chairman, President and CEO. 3: Peter Ehlig, P.E., Fellow DSP, Semiconductor Group. 4: Dan Shimizu, AMD Fellow. 5: Glenn Perry, General Manager, ESL and Design Creation Division. 6: James T. Healy, LogicVision, Inc., President and Chief Executive Officer. Opportunity to Win an iPod shuffle During this Panel Discussion . . . Don't Miss Out!
		Steve Leibson, Technology Evangelist, Tensilica Corporation. Panelist Bio: Steve Leibson is an experienced hardware and software design engineer, engineering manager, and design consultant. He spent 10 years working at electronic systems companies including HP’s Desktop Computer Division, Auto-Trol Technology (graphics workstations), and Cadnetix (EDA workstations) after earning his BSEE cum laude from Case Western Reserve University. At HP, Auto-Trol, and Cadnetix, he specialized in the design of desktop computers and workstations, especially in the areas of system and I/O design. He then spent 15 years as an award-winning technology journalist, publishing more than 200 articles in Microprocessor Report, EDN, EE Times, Electronic News, and the Embedded Developers Journal. He served as Editor in Chief of both EDN and the Microprocessor Report and was the founding Editor in Chief of the Embedded Developers Journal. Leibson has just written and published “Designing SOCs with Configured Cores,” a treatise on 21st-century MPSOC design. Twenty years earlier, he wrote and published “The Handbook of Microcomputer Interfacing,” which was published in English, French, and Dutch, and was used as a university textbook for many years. In 2004, he co-authored “Engineering the Complex SOC” with Tensilica’s president and CEO Chris Rowen, which has also been used as a textbook in university classes. He has also contributed chapters to several other SOC design books since joining Tensilica in 2001.
		Jack Harding, Chairman, President and CEO, eSilicon. Panelist Bio: Jack Harding brings more than 20 years of executive management experience in the electronics industry to eSilicon. Prior to co-founding eSilicon, he served as president and CEO of Cadence Design Systems; during his tenure, Cadence was the world's largest supplier of electronics design software. Previously, Harding was president and CEO of Cooper & Chyan Technology, which was acquired by Cadence in 1997. Harding also served as Executive Vice President of Zycad Corporation. He began his career with distinction at IBM. Harding earned his bachelor's degree in Economics and Chemistry from Drew University and has served as Vice Chairman of its Board of Trustees. He is a Senior Fellow at the Institute for Development Strategies for the School of Public and Environmental Affairs at Indiana University. Harding is a member and former Steering Committee member of the Council on Competitiveness, a Washington, D.C. based organization dedicated to the global competitiveness of the U.S.; and a former National Academies' Committee member for Software, Growth and the Future of the U.S. Economy. He is a frequent lecturer on innovation and entrepreneurship, and has served on many boards of public and private companies. He is a member of Board of Directors for RF Micro Devices (RFMD). In 2007, the industry elected Mr. Harding to the Board of Directors for the Global Semiconductor Alliance (GSA).
		Peter Ehlig, P.E., Fellow DSP, Semiconductor Group, Texas Instruments. Panelist Bio: Peter has worked at Texas Instruments for over 30 years. In this time he has worked in areas varying from operating systems to CPU architecture definition to semiconductor material science. He has inventions involving in Modems, Cell Phones, Hard Disk Drives, Automotive, and Military applications. He believes SOC success involves at least a working understanding of the end customer’s needs and interests all the way down to the semiconductor physics of the device or devices.
		Glenn Perry, General Manager - Mentor Graphics ESL and Design Creation Division. Panelist Bio: Glenn Perry has served as the General Manager of the ESL-HDL Design Business Unit at Mentor Graphics since 2004. He joined Mentor in 1999 as the engineering director for system level simulation tools, bringing over 20 years of experience in the electronics industry, focused in the simulation and analysis of Systems and IC Design. Prior to Mentor, Perry held engineering and management positions at Analogy(now Synopsis), Harris Semiconductor, Sandia National Laboratories and the United States Air Force Weapons Laboratory. Perry studied electrical engineering in the USAF and University of New Mexico.
		Dr. Fadi Maamari, Chief Operating Officer, LogicVision. Panelist Bio: Fadi Maamari, Ph.D., Chief Operating Officer, has been with LogicVision since 1996 and has helped develop several generations of its embedded test technology. He has served as LogicVision’s Vice President of Engineering since June 2006, and previously held senior management positions in Engineering, Applications Engineering and Marketing. From 1990 to 1996, Dr. Maamari was a Member of Technical Staff at AT&T Bell Labs’ Engineering Research Center in Princeton, NJ, specializing in Computer-Aided Design-For-Test of Integrated Circuits. He has a Ph.D. from McGill University in Montreal, and M.S. and B.S. Engineering degrees from École Polytechnique in Montreal, Canada.
	2:00 - 2:30 Keynote Intel	Pranav Mehta, Sr. Principal Engineer and CTO, Embedded & Communications Group, Intel. Keynote Abstract: Following the theme of the 2008 conference, “Innovation in Chip Design,” Schooler will address how System-on-Chip (SoC) technology has evolved from traditional, three-chip solutions and how SoCs eliminate design barriers and increase performance for various compute platforms. Schooler will also discuss power reduction and management techniques at the architectural, design and physical levels for SoCs. The keynote will also look at new usage models enabled by SoC designs and customer benefits, such as decrease in time-to-market, ability to design products using the same board and cost savings. Finally, Schooler will speak to design challenges that led to the development of current SoC products and how these key learnings can be applied as best practices in the engineering field. Key take-aways for the audience include: • Realize performance enhancements enabled by modern SoCs • Understand design challenges that spurred SoC innovation • Learn case study for SoC designs with scalability for more than one application • Gain insight into the future of SoC technology and potential applications Bio: Pranav Mehta, Sr. Principal Engineer and CTO, Embedded & Communications Group, Intel. Pranav Mehta is a Sr. Principal Engineer and CTO for the Embedded & Communications Group within Intel’s Digital Enterprise Group. His team focuses on optimizing the Embedded Intel Architecture (IA) building blocks for the Communications, Storage, and Embedded market segments. This involves understanding performance bottlenecks in IA CPU and System architectures for these application segments; developing solutions to remove those bottlenecks; and modeling these solutions to ensure proper ROI before incorporating them into IA silicon. He has led architecture development of several embedded IA chipsets and SOCs.
	2:30 ‒ 3:00 Tensilica	Steve Leibson, Technology Evangelist, Tensilica Corporation. "Convenient Concurrency Rules Multicore SOC Design." Abstract: The former lords of multiprocessing in the supercomputing realm call problems that are easily decomposed for distribution to multiple processors “embarrassingly parallel,” as though you should be embarrassed when you need not break your back to solve a problem. Well-known problems such as graphics and network packet processing exhibit this type of parallelism. However, even embarrassingly parallel problems can require some pretty elegant solutions. Fortunately, there’s a lot more parallelism around than is implied in the term “embarrassingly parallel.” In fact, my colleague Grant Martin, Tensilica’s Chief Scientist, coined a new term to describe this situation: “conveniently concurrent.” Conveniently concurrent problems surround us. Even problems formerly considered embarrassingly parallel are conveniently concurrent. Many SOCs destined for high-volume consumer products exhibit plenty of convenient concurrency. Intel and AMD are both pushing multicore processors in the PC space these days. They must because the clock-rate wars have ended due to excessive power dissipation. The same is happening in the world of SOC design. In the PC space, all of the old rules from supercomputing days are seeping in and people are searching for compilers that will decompose big problems into processor-sized chunks. We are much more fortunate in the embedded world. Abundant concurrency is arranged so that the problem naturally decomposes into several processor-sized chunks. This talk will discuss just how conveniently convenient this situation is and how these factors influence multicore SOC design. Bio: Steve Leibson is an experienced hardware and software design engineer, engineering manager, and design consultant. He spent 10 years working at electronic systems companies including HP’s Desktop Computer Division, Auto-Trol Technology (graphics workstations), and Cadnetix (EDA workstations) after earning his BSEE cum laude from Case Western Reserve University. At HP, Auto-Trol, and Cadnetix, he specialized in the design of desktop computers and workstations, especially in the areas of system and I/O design. He then spent 15 years as an award-winning technology journalist, publishing more than 200 articles in Microprocessor Report, EDN, EE Times, Electronic News, and the Embedded Developers Journal. He served as Editor in Chief of both EDN and the Microprocessor Report and was the founding Editor in Chief of the Embedded Developers Journal. Leibson has just written and published “Designing SOCs with Configured Cores,” a treatise on 21st-century MPSOC design. Twenty years earlier, he wrote and published “The Handbook of Microcomputer Interfacing,” which was published in English, French, and Dutch, and was used as a university textbook for many years. In 2004, he co-authored “Engineering the Complex SOC” with Tensilica’s president and CEO Chris Rowen, which has also been used as a textbook in university classes. He has also contributed chapters to several other SOC design books since joining Tensilica in 2001.
	3:00 ‒ 3:30 Toshiba	Hideki Takeda, Senior Specialist, Center for Semiconductor Research & Development Semiconductor Company Toshiba Corporation. "Venezia, a New Scalable Multicore Processor for Mobile Multimedia Applications." Abstract: Toshiba will introduce a new scalable multi-core processor, Venezia, for the mobile multimedia systems. Venezia is organized by small and low-power processors that are configured by Toshiba’s configurable processor MeP (Media embedded Processor). By changing number of processors and size of caches, it can cover a broad range of applications from low-end to high-end. Furthermore, Venezia’s software platform enables the binary level software compatibility and performance scalability among variety of designs based on Venezia architecture by exploiting coarse-grain thread level parallelism. Bio: Hideki Takeda received the B.S. degree in Electrical Engineering and M.S. degree in Electronic Engineering from the University of Tokyo, Tokyo, Japan in 1992, 1994, respectively. In 1994, he joined Toshiba Corporation, where he has been engaged in the development of MPEG-2/H.264 decoder LSIs, media processors. He is currently involved in the development of video codec LSI for mobile multimedia system.
	3:30 ‒ 4:00 National Taiwan University	Professor Sao-Jie Chen, National Taiwan University "DESIGN OF A VLIW/SMT/DUAL-CORE SWP-SIMD PLX2 PROCESSOR." Abstract: In embedded multimedia systems, increasing operations per cycle and reducing clock frequency in a design are the key concepts to reduce its energy consumption. Subword-parallel Single-Instruction Multiple-Data (SWP-SIMD) processor provides a low-cost high-performance solution for multimedia applications. But there still exist some critical sequential algorithms that could not be improved by SWP-SIMD. Using VLIW to increase Instruction-Level parallelism (ILP) or simultaneous multi-threading (SMT) to hide memory latency is useful for these algorithms. Our newly designed 64-bit SWP-SIMD core can be partitioned into two 32-bit scalar ALUs, working as a two-issue VLIW core or a dual-core. This multi-mode parallelization capability allows more performance improvement with little hardware cost increase. Bio: Sao-Jie Chen received the B.S. and M.S. degrees in electrical engineering from the National Taiwan University, Taipei, Taiwan, ROC, in 1977 and 1982 respectively, and the Ph.D. degree in electrical engineering from the Southern Methodist University, Dallas, USA, in 1988. Since 1982, he has been a member of the faculty in the Department of Electrical Engineering, National Taiwan University, where he is currently a full professor. During the fall of 1999, he was a visiting professor in the Department of Computer Science and Engineering, University of California, San Diego, USA. During the fall of 2003, he held an academic visitor position in the Department of System Level Design, IBM Thomas J. Watson Research Center, Yorktown Heights, New York, USA. During the falls of 2004, 2005, 2006, and 2007, he was a visiting professor in the Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA. His current research interests include: VLSI physical design, SOC hardware/software co-design, and Wireless LAN and Bluetooth IC design. Dr. Chen is a member of the Chinese Institute of Engineers, the Chinese Institute of Electrical Engineering, the Institute of Taiwanese IC Design, the Association for Computing Machinery, a senior member of the IEEE Circuits and Systems and the IEEE Computer Societies.
	4:00 - 4:15 Afternoon Break	Afternoon Break
	4:15 - 4:45 UCI	Dr. Nader Bagherzadeh, University of California, Irvine. "General Purpose Processors (GP) vs. Application Specific Processors (ASP), what is the future for multicore designs with 1000's of IPs?" Abstract: In this talk first a brief overview of multicore architectures is discussed. Next, the critical issue of homogeneous versus heterogeneous processing nodes for the future multicore architectures is analyzed, and areas that require further research and development are identified. Finally. concluding remarks are made regarding future designs. Bio: Dr. Nader Bagherzadeh has been involved in research and development in the areas of computer architecture, reconfigurable computing, VLSI chip design, and computer graphics. For almost ten years ago, he was the first researcher working on the VLSI design of a Very Long Instruction Word (VLIW) processor. Since then, he has been working on multithreaded superscalars and their application to signal processing and general purpose computing. His current project at UC, Irvine is concerned with the design of coarse grain reconfigurable pixel processors for video applications. The proposed architecture, called MorphoSys, is versatile enough to be used for digital signal processing tasks such as the ones encountered in wireless communications and sonar processing. DARPA and NSF fund the MorphoSys project (total support $1.5 million). Dr. Bagherzadeh was the Chair of Department of Electrical and Computer Engineering in the Henry Samueli School of Engineering at University of California, Irvine. Before joining UC, Irvine, from 1979 to 1984, he was a member of the technical staff (MTS) at AT&T Bell Laboratories, developing the hardware and software components of the next-generation digital switching systems (#5 ESS). Dr. Bagherzadeh holds a Ph.D. in computer engineering from The University of Texas at Austin. As a Professor, he has published more than a hundred articles in peer-reviewed journals and conference papers in areas such as advanced computer architecture, system software techniques, and high performance algorithms. He has trained hundreds of students who have assumed key positions in software and computer systems design companies in the past twelve years. He has been a Principal Investigator (PI) or Co-PI on more than $2.5 million worth of research grants for developing next-generation computer systems for solving computationally intensive applications related to signal and image processing.
	4:45 ‒ 5:15 MIPS Technologies	Darren Jones, Engineering Director, Microprocessor Development MIPS Technologies, Inc. "Boosting System Performance with Multithreaded Multiprocessing." Abstract: Today’s SMP operating systems and coherent multi-core platforms offer developers a performance migration roadmap under one OS and the potential to make better use of system resources—maximizing SoC performance on mainstream silicon processes and clock speeds. Adding multithreading on top of a coherent multi-core architecture extracts even more performance by optimizing pipeline utilization in each CPU for minimal additional silicon cost. The performance boost comes essentially for “free” in both hardware and software, since the additional hardware threads are minimal in size relative to a typical SoC design, and multithreading uses the same SMP OS and software programming models as coherent multi-core platforms. In some applications, multithreading can reduce the need for additional processors, or may help achieve an application performance target at lower frequency and/or a smaller synthesized design. This presentation will discuss real-world applications of MIPS Technologies’ MIPS32® 1004K™ coherent processing system—the industry’s first embedded multithreaded, multiprocessor licensable IP core—including the latest performance benchmarking data. Bio: As Engineering Director, Microprocessor Development, Darren Jones is responsible for the logic design of MIPS Technologies’ 32-bit processor core families including the high-performance 24K and 24KE cores, multi-threaded 34K cores and multi-threaded multiprocessing 1004K cores. Darren joined MIPS Technologies in 1998 from LSI Logic, where he held the position of Engineering Manager. During his tenure at MIPS Technologies and LSI, he has worked on ten different cores, always using an ASIC-style/reusable IP methodology. Darren graduated from the University of Illinois in 1989 with a BSEE, and received his MSEE from Stanford University in 1990.
	5:15 - 5:45 ST Microelectronics	Antonio-Marcello Coppola, Head of the Grenoble Research Laboratory, ST Microelectronics. "Is the "true NoC" just an urban engineering legend?" Abstract: Recently, most major PC industries as well as embedded devices are shifting to multiple cores (Multicore) on a single chip to improve processor performance. This presentation will discuss the evolution of Multicore for mobile consumer applications from a different angle. It will show the importance that an on-chip communication network is playing during this evolution and trying to see if future Multicore architectures will include or not a true NoC. Bio: Marcello Coppola is working for STmicroelectronics, he is Head of the Grenoble Research Laboratory within “Advanced System Technology”, a corporate research organization in ST. He studied computer science at Pisa University. In 1992, he received his Laurea degree and started working at the Transputer architecture group of INMOS, Bristol (UK). For 2 and half years he worked on a research program regarding the architecture of the C104 router. His research interests include several aspects of design technologies for System on Chip, with particular emphasis to Network on Chip, MPSoC architecture, Programming Modeling and system level design. His publication record covers publications in the filed of simulation, modeling, SoC architecture and on-chip communication network. He wrote chapters for different books. He was one the members for the OSCI language working group. He contributed to SystemC2.0 language definition and OSCI standardization. He has chaired international conferences on SoC design and helped to organize several others. He is program committee member of DATE, FDL, CODES+ISSS, DAC. He is cited in Marquis “Who’s Who in Engineering” and IBC biographies.
	4:30 pm - 8:30 pm Exhibit	Conference Exhibit & Reception Open


	8:00 - 8:15	Farhad Mafie, President and CEO of Savant Company Inc. "Welcome and Opening Remarks, Technology/Market Trends." Farhad has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. Farhad is the former Vice President of Marketing/Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing the entire Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth, Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.). He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer products & solutions based on ASSP and SoC Models. Farhad established Toshiba's on-line Tech-Support System as well as Toshiba's on-line System Solution Selling methodologies for all Toshiba's products in the North American markets. These on-line systems were adopted by Toshiba on a worldwide basis. He also developed Toshiba's ASSP Business Unit and Technical Sales Engineering Team as two brand new organizations for the company. Farhad has also worked at Lucent Technologies on marketing communications ICs, Toshiba Information Systems on product definition for Toshiba's notebooks and handheld products, Unisys on designing new processors and computer systems, and MSI Data on designing data collection products. He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. His combined business and academic experience has given Farhad a unique ability to effectively communicate complex new technologies to business professionals at all levels, as well as the ability to foresee emerging leading-edge technologies. Farhad is an author and a translator, and he writes articles for a variety of journals and Web-based magazines on technology and political affairs.
	8:15 am - 12:00 am	Innovative Embedded Memory Solutions for Complex Multicore SoCs Track Chairman: Dr. Nader Bagherzadeh, University of California, Irvine.
	8:15 - 8:45 GENUSION	Moriyoshi Nakashima, President, GENUSION. "NVM Technologies - B4-Flash with its Embedded Application and eCFlash (Logic NVM IP)" Abstract: In the recent non-volatile memory (NVM) arena, NVM technology has been expanding the applications of data storage with NAND Flash. On the other hand other types of NVM applications have been generated in SoC, MCU and all kind of LSI devices by embedded NVM technologies for built-in program storage, security or tuning data. In consequence, many types of memory technologies have been proposed to meet with and to be optimized for individual customer requirements regarding application, cost, density, performance, and so on. It seems to be diverging of NVM technologies in the embedded NVM arena. GENUSION proposes a novel NVM technology “B4-Flash” for code storage which achieves higher performance and reliability with lower cost in comparison with conventional NOR. We propose the embedded NVM IP portfolio to apply wide range of customer requirements with our embedded NVM technology platform of B4-Flash and another GENUSION proprietary NVM of eCFlash as logic NVM. Bio: Moriyoshi Nakashima joined Mitsubishi Electric Corporation in 1981. He had been in charge of non-volatile memory process integration and technology development including embedded NVM applications until 1998. He became the manager of flash memory business unit in 1998 to start memory solution and multi chip package (MCP) business for mobile phones leading to one billion US dollar business and world biggest MCP share in the application. He quitted Mitsubishi in 2002 and founded GENUSION. He is a president of GENUSION, Inc. developing novel NVM technologies.
	8:45 - 9:15 Kilopass Technology	Charles Ng, VP of Worldwide Sales & Marketing, Kilopass Technology Inc. "Demystifying Logic NVM Options." CMOS Logic NVM IP solutions each have advantages and disadvantages that hinge on their respective underlying technologies. In this presentation, an introduction will be made for the three types of Logic NVM technologies in production today: fuse, antifuse, and floating gate. Each technology will be described in terms of its capabilities as an embedded NVM technology. Based on each technology analysis will also be provided regarding process trends and the future of CMOS Logic NVM for SoC applications. Bio: TBD.
	9:15 - 9:45 Micron	Jim Cooke, Staff Architect and Technologist, NAND Flash. Micron Technology. "Achieving the Need for Speed in Flash Based Designs." Abstract: Data rates for many next generation flash interfaces, like USB 3.0, C-Fast and others, will exceed 300MB/s, but today’s flash interfaces typically support only 10 to 40MB/s. Traditional techniques to achieve higher performance, like wider data busses, are not always an option and can cause density issues. This presentation will discuss new NAND flash standards and devices that will support increased data rates. In addition, we will discuss migration paths and backwards compatibility with traditional NAND flash interfaces. We will include specifics of the interface, signal integrity and implementation details that will provide designers with all the tools that are needed to implement high performance systems. We will also discuss Flash technology trends and the future challenges in 32nm and beyond. Bio: Jim Cooke is a Staff Architect for Micron’s architecture development group. He has a BSEE from the University of Massachusetts. Previously, he was responsible for managing the applications engineering group and hardware engineering team for Toshiba America Electronic Components. In addition, Jim has over 20 years of hands-on systems-level design experience in embedded applications and digital consumer markets.
	9:45 - 10:00 Morning Break	Morning Break
	10:00 - 10:30 Keynote Georgia Institute of Technology	Professor Rao R. Tummala, Director of Microsystems Packaging Research Center. Georgia Institute of Technology. "An All Silicon 3D Systems Technology, An Emerging and Disruptive Technology for Convergence of IC, Package and System," Abstract: 3DASSM is an all Silicon System using Si for ICs, components, packages and system boards using 3D technologies. It is an ultra-miniaturized, ultra-functional, and low cost systems technology, enabled by new designs, thin-film materials, large-area low-cost processes, and heterogeneous functional integration leading to lower cost convergent system products. Such a technology is presented as achieving better electrical performance, ultra-miniaturization, greater heterogeneous integration, higher thermal performance and higher thermo-mechanical reliability at lower-than-today's organic-based hybrid packages and systems. This technology is proposed as an R&D industry consortium in partnership with Fraunhofer (Germany) and KAIST (Korea) and includes exploratory interdisciplinary fundamental research in design and test, Si package replacing organic package, low cost TSV and stack bonding, thin-film embedded active and passive components, and system interconnections. In addition, the consortium integrates the above fundamental research into useful test vehicles to demonstrate the commercial feasibility of cost effective 3D structures, silicon packages, and all silicon modules with seamless integration of ICs with their FEOL and BEOL, as well as with package wiring. More than 20 projects are proposed in these areas. 3DASSM differs from other 3D industry programs in a variety of ways, such as: 1. 3DASSM starts with the current industry problem, the high cost and low reliability of TSV and stack bonding. Here we propose several fundamental research projects to address cost and reliability, such as new fabrication methods for low cost and high density TSVs, new structures that improve the rmomechanical reliability, novel low cost solder and adhesive stack bonding methods. In addition, this research will culminate in a 3D stack bonding test vehicle and a Si package test vehicle to demonstrate the improved performance, reliability, and manufacturability of the technologies developed. 2. 3DASSM goes beyond current 3D programs to demonstrate a double-sided silicon package replacing the organic package enabled by low cost TSV in a seamless integration. This test vehicle will address shortcomings of the organic package such as wiring and I/Os, thermal performance, warpage and cost. 3. 3DASSM leads to next generation of wafer level packaging. This is referred to as Wafer System module in the 3DASSM. In this approach, ICs with both FEOL and BEOL are integrated with seamless integration of package wiring and cost effective thin embedded components on both sides of wafer enabled by TSV and 3D interconnections. The ultimate goal is to design, demonstrate and commercialize a highly integrated all silicon system module (ASSM). 3DASSM, therefore, is a global Industry-Academia consortium on a global topic with potential to become a disruptive and revolutionary silicon module technology in the near term and a systems technology in the long term. Bio: r. Rao Tummala received the BE degree in Metallurgical Engineering from the Indian Institute of Science, Bangalore, India and the Ph.D. degree in Materials Science and Engineering from the University of Illinois. He joined the faculty at Georgia Tech in 1993 as a Pettit Chair Professor in Electronics Packaging and as Georgia State Research Scholar. He is also the Director of the Microelectronic Systems Electronic Packaging Research Center funded by NSF as one of its Engineering Research Centers, the state of Georgia, and US electronics industry. Prior to joining Georgia Tech, he was an IBM Fellow at the IBM Corporation, where he invented a number of major technologies for IBM's products for displaying, printing, magnetic storage and multichip packaging for which he received 16 Technical, Outstanding and Corporate Awards from IBM. He is both a fellow of IEEE and the American Ceramic Society, a member of the National Academy of Engineering, 1996 President of IMAPS and current president of the IEEE-CPMT Society. He was recently named by Industry Week as one of the 50 Stars in the US, for improving US competitiveness. He is co-editor of four widely-used Microelectronics Packaging Handbooks. He published 205 technical papers and holds 68 US patents and inventions. He has received many awards: David Sarnoff, sustained technical achievement award from IEEE, John Wagnon's award from IMAPS, Materials Engineering achievements award from ASM-I, Distinguished Alumni Honor award from University of Illinois and the Indian Institute of Science, and Arthur Friedberg Memorial award and the John Jeppson Award from American Ceramic Society, the Total Excellence in Electronics Manufacturing (TEEM) Award from the Society of Manufacturing Engineers, and the European Materials Award from DVM. He recently received the highest faculty award at Georgia Tech, the Distinguished Faculty Award.
	10:30 - 11:00 Innovative Silicon	Jeff Mitchell, Director of Technical Marketing, Innovative Silicon. "Z-RAM: A Better DRAM." Abstract: After nearly 40 years of evolution, the classical 1T/1C DRAM is finally reaching its scaling limit. As a possible replacement technology, Floating-Body Memory is getting increasing industry attention. Z-RAM is a type of Floating-Body Memory which uses a novel method of reading and writing to the memory cell utilizing the bipolar device intrinsic to the MOS transistor. Taking advantage of this "bipolar operating mode" of a Floating-Body Memory increases the operating margins of the memory cell. This substantially improves its manufacturability and creates, for the first time, a truly viable candidate for replacement of the 1T/1C DRAM. Bio: Jeff Mitchell is Director of Technical Marketing at Innovative Silicon. He has more than 20 years of experience in the electronics industry and has been awarded several patents. He has had a varied career, holding positions in engineering, marketing, and business development. Mitchell has a B.S. in Engineering from Harvey Mudd College.
	11:00 - 11:30 Virage Logic	Luigi Ternullo, Product Marketing Manager, STAR Memory System, Virage Logic Corporation "Using Data Traffic Efficiency Metrics to Select the Best DDR Memory Controller for your Design." Abstract: The use of DRAM has become a key architecture consideration for many System-on-Chip (SoC) designs. Whether the DRAM is designed to be on-chip (embedded DRAM), or an off-chip DRAM subsystem, the SoC will very likely require an on-chip memory controller, and many times an IP-based memory controller is used. Understanding how to select the best IP-based memory controller for specific applications can be a complex task. Some of the obvious criteria, such as performance, area, cost, power, and latency all need to be factored in, however, using a data traffic “efficiency” metric (bandwidth delivery/theoretical maximum bandwidth) has proven to be the most important criteria for a wide range of applications. This paper will describe the efficiency metric and will show measurements for typical efficiency levels that can be achieved for different memory controller architectures. This will make it easier to determine where in the efficiency spectrum a particular memory controller design resides. Additionally, we will use two examples from real systems (a networking router and an image processor for a security application), to demonstrate how efficiency can be used to make system tradeoffs that can result in significant savings, lower system cost, lower power consumption, gain higher system performance, and quicker time-to-market. Bio: Luigi Ternullo serves as Product Marketing Manager for Virage Logic’s Application Specific IP product solutions such as Double Data Rate (DDR) memory controllers. Prior to joining Virage Logic in 2006, Ternullo held technical marketing management positions and senior engineering management positions at Agere, Vanguard International Semiconductor, and IBM. His range of experience includes SRAM design, memory and logic built-in self-test (MBIST and LBIST). Mr. Ternullo also holds over 25 patents in BIST and memory design, and has authored several BIST papers. He holds a B.S. and M.S. in Electrical Engineering from Rochester Institute of Technology, and M.B.A. from Lehigh University.
	11:30 - 12:00 Novelics	Esin Terzioglu, Ph.D., Chief Technology Officer and Co-Founder, Novelics Corporation. "Innovative Embedded Memories." Bio: Novelics co-founder Esin Terzioglu serves as chief technology officer for the company, overseeing technical strategy, hiring and organization. Dr. Terzioglu is responsible for managing the engineering projects and innovations for the company’s embedded memory technologies.Prior to co-founding Novelics, Dr. Terzioglu held key technical positions at Broadcom Corporation from 1999 to 2005, progressing from staff scientist to principal scientist. He led the development of four generations of embedded SRAM memory technology, contributing to industry-leading achievements in memory area efficiency, power and speed. Dr. Terzioglu has published 11 technical papers in the areas of fabrication processes, device physics and superconducting electronics, and holds more than 50 patents, mainly in circuit design and semiconductor memory technologies. Dr. Terzioglu received his bachelor’s of science in electrical engineering from the University of Rochester, his master’s of science and his Ph.D. in electrical engineering from Stanford University with a minor in computer science.
	12:00 - 1:00 Lunch	Lunch
	1:00 - 2:00 Panel	Panel: "Innovative Embedded Memory Solutions for Complex Multicore SoCs”
	Chip Design Tohoku University MOSAID Crocus Technology Novelics ARM KeyASIC	John E. Blyler, Editorial Director Chip Design, Embedded Intel, Green Embedded and EE Catalog magazines. Moderator John is the Editorial Director for Extensionmedia. He provides editorial direction for Chip Design, Embedded Intel and Green Electronic System print/online magazines, in addition to Trends reports. John was the senior editor for Penton s Wireless Systems Design magazine and the IEEE I&M magazine. John has co-authored several books on technology (Wiley and Elsevier). He has over 23 years systems engineering hardware-software experience in the electronics industry. John remains an affiliate professor in Systems Engineering at Portland State University. Mr. Blyler holds a BS in Engineering Physics from Oregon State University, as well as a MSEE from California State University, Northridge. He maintains a blog at: www.chipdesignmag.com/blyler Panelists 1: Dr. Mitsumasa Koyanagi, Distinguished Professor, Graduate School of Engineering, Dept., of Bioengineering and Robotics Advanced Bio-Nano Devices Lab. 2: Dr. Dick Foss, Founder and former Chairman of MOSAID. 3: Jean-Pierre Nozieres, Founder and CTO. 4: Dr. Cyrus Afghahi, CEO, Novelics. 5: Dr. Robert C. Aitken, Fellow, R&D. 6: Alan Aronoff, Vice President of Business Development. Opportunity to Win an iPod shuffle During this Panel Discussion . . . Don't Miss Out!
		Dr. Robert C. Aitken, Fellow, R&D, ARM Corporation. Panelist Bio: Robert C. Aitken is an R&D Fellow at ARM. His areas of responsibility include library architecture, low power design, and design for manufacturability. He has given tutorials and short courses on several subjects at conferences and universities worldwide. He has published over 50 technical papers, and holds a Ph.D. degree from McGill University in Canada.
		Dr. Virgile Javerliac, MRAM Memory design and Technology Interface for Crocus Technology. Panelist Bio: Virgile Javerliac holds an Electrical Engineering degree from the Superior Institute of Microelectronic (Marseille) part of the School of Mines (Saint-Etienne) and a PhD in Micro and Nano Electronic from the Grenoble Institute of Technology (INPG in French). Virgile has worked during its PhD on CMOS-MRAM physical IPs design for MRAM-Based reconfigurable logic blocks architectures at CEA-LETI-Spintec laboratories. He joins Crocus Technology in 2006 Technology as a Memory designer in Silicon Valley and support also with the CEA the MRAM SPICE-PDK project development. He is the inventor of many international patents on MRAM, MRAM-Based Physical Logic Blocks, MRAM-Based Ternary CAM and has authored/co-authored scientific publications on MRAM-Based FPGA and SPICE modeling.
		Alan Aronoff, Vice President of Business Development, KeyASIC. Panelist Bio: Alan Aronoff – Vice President, Marketing and Business Development, KeyASIC. Alan Aronoff brings more than 25 years of semiconductor and IP experience to Key ASIC. At Key ASIC, he developed the business model and IP portfolio for Key ASIC that has focused on consumer electronics applications. Prior to co-founding Key ASIC in 2005, he served as Vice President and General Manager of the Silicon Library Business Unit for Synopsys, Inc., and as General Manager of the ASIC Business Unit for NEC Electronics, Inc. Aronoff was a founder of the ASIC business at Mostek Corporation. He earned a Bachelors of Science Degree in Electrical and Biomedical Engineering from Carnegie-Mellon University and a Masters of Science degree in Electrical Engineering from Southern Methodist University.
		Dr. Cyrus Afghahi, CEO, Novelics. Panelist Bio: Cyrus Afghahi co-founded Novelics in 2005 with a vision of dramatically enhancing embedded memory performance in semiconductor design. With more than 20 years of experience as a semiconductor industry professional, Dr. Afghahi has led strategic technology initiatives in low-power and high-speed very large-scale integration (VLSI) designs for advanced, high-performance applications. Prior to co-founding Novelics, Dr. Afghahi was technical director for the Office of the Chief Technology Officer at Broadcom Corporation, where he was involved in strategic special circuit and design decisions. Before joining Broadcom, Dr. Afghahi held key technical and management positions at Intel Corporation, Ericsson Radio and Carlsted. At Intel he was responsible for RF circuit design and served as technical manager of high-performance sensor chips and memories. He received his Ph.D. in electrical engineering from University of Linkoping, Sweden. Dr. Afghahi holds more than 60 patents and has published 20 journal and conference articles.
	2:30 - 5:45	Innovative EDA Tools for Complex SoC Designs in 45nm and beyond. Track Chairman: Track Chairman: Professor Rao R. Tummala, Director of Microsystems Packaging Research Center. Georgia Institute of Technology.
	2:00 - 2:30 Keynote Synopsys	Joachim Kunkel, VP and General Manager, Solutions Group, Synopsys. "Automating SoC Design - Reality, Future, or Fiction?" Abstract: Designing SoCs has often been described as an activity based on taking building blocks - some new, many already existing - and putting them together following a set of rules and constraints. The concept sounds simple, compelling and, in particular, one that could be automated by tools working at a high level of abstraction. If this is the case, how comes we are still seeing very little automation of SoC design? This talk will examine the current state of affairs of automating the design of SoCs and make an attempt at predicting the future. Bio: Joachim Kunkel is the Vice President and General Manager of the Solutions Group at Synopsys, Inc. In that capacity, he manages the business units responsible for Synopsys DesignWare® intellectual property (IP) and system-level design. Prior to joining Synopsys in 1994, Joachim was a managing director of CADIS GmbH, a company he had co-founded in 1989 in Aachen, Germany. CADIS GmbH focused on the development of system level design tools for digital signal processing and providing specialized design services for wireless communication systems. From 1984 to 1989, Joachim was a research assistant at the Aachen University of Technology’s ‘Lehrstuhl fuer Elektrische Regelungstechnik’, where he conducted research in the area of system level simulation techniques for digital signal processing, with special emphasis on parallel computing. Joachim holds an MSEE from the Aachen University of Technology, Aachen, Germany.
	2:30 - 3:00 Mentor Graphics	Jon McDonald - Senior Technical Marketing Engineer, ESL and Design Creation Division, Mentor Graphics. "Leveraging ESL Technologies for Low-Power Design." Abstract: Designs for managing and optimizing power are a key concern for today's electronics companies, and the only way to address future power needs is through architecture and functional-aware techniques. Electronic System Level (ESL) design is the only domain that offers a practical platform to address today's power design issues. This 30-minute technical session will introduce a dynamic power management theory , functional-aware optimization, HW/SW tradeoffs, and an approach to design for power, applying available ESL technologies. Included, will be a couple of case-studies to support these key points. This technical session will be of value to SoC developers, HW and SW designers, followed by a Q/A session with the presenter (if available). Bio: Jon McDonald is a senior technical marketing engineer for Mentor Graphics ESL division. He received a BS in Electrical and Computer Engineering from Carnegie Mellon and an MS in Computer Science from Polytechnic University. He has been active in digital design, language based design and architectural modeling for over 15 years. Prior to joining Mentor Graphics Mr. McDonald held senior technical engineering positions with Summit Design, Viewlogic Systems and HHB Systems.
	3:00 - 3:30 Sarnoff Europe	Benjamin Van, Director of Engineering, Sarnoff Europe, “ESD Design Challenges in nano-CMOS SoC Design” Abstract: IC's created in 90nm, 65nm and 45nm are typically very complex System On Chip (SOC) designs with large production volume to offset the multi-million dollar investment for mask costs, innovation and design. Such SoC's combine multiple voltage domains as well as different functional blocks. Despite the use of a complete and silicon proven ESD protection strategy for core and IO pads, companies have repeatedly reported failures in the (logic) core of the IC during ESD - and particularly during CDM- testing. This presentation will elaborate on these and similar unexpected failures and will include clarifications, focusing on the ESD damage created at the communication lines between different functional domains in the SoC. Through the use of IC case studies, the presentation will demonstrate the ESD sensitivity in similar designs. A product proven protection strategy and specific ESD solutions will be presented to the audience. Bio: As “Director of Engineering” at Sarnoff Europe, Benjamin Van Camp currently leads the entire engineering team at the company. He is also responsible for the strategic development of TakeCharge®, the portfolio of on-chip ESD design solutions – product and/or silicon proven in more than 40 processes down to 45nm. Prior to assuming his current position, Benjamin served as director for commercial products. In this position, he was involved in a multitude of complex and innovative ESD projects, and collaborated with Sarnoff customers on cutting-edge innovative products. Benjamin has (co-) authored about 10 peer-reviewed and published articles in the field of “on-chip ESD protection and testing”, and has acted in various workshops focusing on ESD. He was awarded his first patent in 2006, with 8 patent applications still pending. Benjamin Van Camp received his M.Sc. degree in Electro-technical Engineering from the University of Leuven, Belgium in 2002.
	3:30 - 4:00 CoFluent Design	Vincent Perrier, co-founder and director of products and marketing, CoFluent Design. "ESL Modeling and Simulation for SoC Architecture and Performance Estimation." Abstract: CoFluent Design introduces a new level of ESL modeling and simulation for the architecture exploration and performance analysis of embedded systems and SoCs, before and at HW/SW partitioning. CoFluent Studio allows the description of a complete HW/SW system at the message level, corresponding to an approximately timed – AT – modeling style. From simple graphics, C code and performance/timing attributes, CoFluent Studio generates automatically SystemC code which simulation results allow for behavioral, real-time, architectural, and performance estimation. CoFluent models do not necessitate embedded SW code, instruction set simulators – ISS – or hardware IPs: they are created from behavioral and generic performance models captured and parameterized by the user. CoFluent Design's method is based on a ‘Y’ design flow that separates the timed-behavioral view from the execution platform view and combines them to obtain a macroscopic architecture model. The Y flow and drag-and-drop mapping allow for unlimited architecture exploration breadth and depth, while performance analysis includes monitoring of dynamic profiles of resource utilization/load, memory footprint, power consumption and cost/Si area indices. Bio: Vincent Perrier is CoFluent Design's co-founder and director in charge of products and marketing. He has over fifteen years of technical, sales and marketing experience in the embedded systems and design automation industries.
	4:00 - 4:15 Afternoon Break	Afternoon Break
	4:15 - 4:45 Carbon Design Systems	Bill Neifert is the CTO and founder of Carbon Design Systems. "Architectural Analysis and Firmware Development for SoC Designs." Abstract: The constant pressure on SoC schedules is forcing designers to constantly re-evaluate their design methodologies looking for ways to shave days, weeks and hopefully months from their time to market. This talk will focus on helping designers reduce their time to market in two areas: the architecture phase where all the early design decisions are made and the software integration phase which is increasingly more important as the software content of SoCs rises. Architectural exploration for SoCs is one of the most crucial stages in a system’s design but its value is often overlooked and relegated to back of the envelope calculations. The design decisions made in the architectural stage however can greatly shorten the amount of work required later in the design cycle. This presentation will cover methods and applications which will enable the architect to make more intelligent design decisions and solve problems early in the design cycle where they have the most impact. Software validation is one of those “no introduction is necessary” problems. Everyone is looking for ways to accelerate their software validation. This presentation will cover methodologies to pull the software schedule earlier in the cycle by performing the software integration task in a presilicon manner on cycle-accurate virtual prototypes of the system. Techniques for accurate validation of hardware and software in a presilicon environment will be covered. Bio: Bill Neifert is the CTO and founder of Carbon Design Systems. Bill has 18 years of electronics engineering experience with more than 15 years in EDA including C-Level Design and Quickturn Systems where he managed technical resources and sales engagements for the eastern half of the United States. Bill started his career as an ASIC design and verification engineer at Bull. Bill has a BS and MS in Computer Engineering from Boston University.
	4:45 - 5:15 NEC	Dr. Kazutoshi Wakabayashi, NEC. "CyberWorkBench: Integrated Design Environment Based on C based Behavior Synthesis and Verification." Abstract: TBD. Bio: Dr. Kazutoshi Wakabayashi, received his B.E. and M.E. degrees and Dr. of Engineering from the University of Tokyo in 1984 and 1986. He was a visiting researcher at Stanford University during 1993 and 1994. He joined NEC Corporation in Kawasaki Japan in 1986 and he is currently a Senior Manager of EDA R&D Center, Central Research Labs. Dr.Wakabayashi has been engaged in the research and development of VLSI, CAD systems; high-level and logic synthesis, formal and semi-formal verification, system-level simulation, HDL, emulation, HLS and floorplan links, and reconfigurable computing. He served on executive committee or organizing committee of some international conference including: ASP-DAC'09 General Chair, CODES+ISSS'09 Co-Technical Program Chair. A Secretary of Steering Committee of ASP DAC, and Asian Rep. of ICCAD, Asian Rep. of DAC, Tutorial Chair of ASP DAC 2006, He has served on the program committees for several international conferences including: DAC, ICCAD, DATE, ASP-DAC, ISSUS, SASIMI, and ITC-CSCC, ISCAS, VLSI-TSI, SBCCI, and so on. Also, he has served as a general chair, a secretary, and a Technical Program Committee member for a number of Japanese conferences, including: Institute of Electronics, Information and Communication Engineers of Japan (IEICE), the Information Processing Society of Japan (IPSJ), System LSI WS, Karuizawa WS. He is currently chair of SIG on VLSI design methodology of IEICE, and elected member of IEICE. He was an associate editor of Transactions on IEICE on VLSI CAD, DAEM. He is a rep. of CEDA (Council for EDA) of IEEE. He is also a member of IEEE, IPSJ, and IEICE. He received the Yamazaki-Teiichi Prize in 2004, and the IPSJ Convention Award in 1988, Sakai Kinen Special Award in 2001, and the NEC Distinguished Contribution Award in 1993 for his logic synthesis system and in 1999 for his formal verification and in 2006 for his High Level Synthesis. His C-based Synthesis and Verification tool suite called "CybeWorkBench" received a Grand prize of "LSI of the Year 2003" and "LSI of the Year 2007".
	5:15 - 5:45 Cadence Design Systems	Tom Anderson, Product Marketing Director, Cadence Design Systems. "Scaling Verification with the Open Verification Methodology (OVM)." Abstract: In the six months since its introduction, the Open Verification Methodology (OVM) has moved into a leading position for functional verification of complex chip designs. There are a number of reasons for its dramatic rise in popularity and deployment, including multi-vendor support, availability as open source, and several technical advantages over legacy methodologies. This talk focuses on one specific advantage of the OVM - its ability to scale during the verification process. This scaling occurs from block to chip to system level, from one project to another, and even from one company to another. The OVM also interacts with verification components written in multiple IEEE-standard languages, including SystemVerilog, e, and SystemC. Further, the OVM has features and benefits of interest to logic designers as well as traditional verification engineers writing complex testbenches. All of these aspects will be explored in this talk, with examples of scaling taken from actual user projects. The focus is on the methodology and its application, not on particular vendors or vendor tools that support the OVM. This talk is appropriate for any design or verification engineer already considering the OVM or simply looking for a better, more scalable verification approach. Bio: Tom Anderson is a Product Marketing Director at Cadence, where he leads a group responsible for all digital simulation and formal analysis products. His previous roles include Director of Technical Marketing at Synopsys, Vice President of Applications at 0-In, and Vice President of Engineering at Virtual Chips. Tom holds an MS from MIT and a BS from the University of Massachusetts at Amherst.
	5:45 – 6:45 Panel	*“Technology & Entrepreneurship: Dreams, Realities & Opportunities”* This Panel is FREE for Everyone to Attend!
	UC Irvine Toshiba IEEE OC Chapter Capistrano Ventures Quanta Consulting Power Connections Crowell & Moring Savant	Dr. Goran Matijasevic is Director of Research Development at The Henry Samueli School of Engineering at UC Irvine Bio: Goran Matijasevic is Director of Research Development at The Henry Samueli School of Engineering at UC Irvine. In this capacity, he works on formation of new industry-university and academic collaborations, especially focusing on new interdisciplinary research initiatives. Prior to this, he was the Research Coordinator of the Integrated Nanosystems Research Facility at UC Irvine, where he worked closely with industry partners on making them aware of available university resources. Prior to UCI, he worked as a senior engineer at QPlus, a telecommunications start-up company. From 1994 to 2001, he was at Ormet Technologies, where as Director of Research he was working on development of polymer and metal materials and structures for electrical interconnect of high density circuits, new metal alloys for use in conductive adhesives, materials for embedded passive components and heat sensors, and high thermal efficiency electronic substrates. ¨He managed multiple SBIR projects that led to several industry consortia projects, as well as a license agreement with a Fortune 100 company. He has 4 U.S. patents, 3 book chapters, and over 40 conference and journal publications and has served on the NEMI Industry Roadmap committee. He served as NanoWorld Conference Technical Chair, the Electronic Components and Technology Conference (ECTC) Interconnect Chair and Emerging Technologies Chair, the IEEE Sensors 2006 Local Chair, the ASME Frontiers in Biomedical Devices Co-Char, as well as on the LARTA Tech Transfer Conference Organizing Committee. He is currently on the OCTANe (Orange County Technology Action Network) Operations Committee and Vice Chair of OC Innovation. Goran received his PhD from UC Irvine in Electrical and Computer Engineering and his MBA from Pepperdine University. He is also a member of the TriTech Advisory Board, Southern California Biomedical Council Board, Tech Coast Venture Network, IEEE, and ASME. “Technology & Entrepreneurship: Dreams, Realities & Opportunities” Moderator: Dr. Goran Matijasevic is Director of Research Development at The Henry Samueli School of Engineering at UC Irvine. Panelists 1: Christopher Harrington, Vice President Strategy & Business Development, Chief CSR Officer, Toshiba America Information Systems. 2: Charles Baecker, Administrative Director, The Don Beall Center for Innovation & Entrepreneurship, The Paul Merage School of Business. 3: Mark Nielsen, Managing Director of Capistrano Ventures. 4: R. Scott Feldmann, Partner. IP Attorney (hardware & Software). 5: R Sampath, Chair, Quanta Consulting, Inc. IEEE OC Section Chairman. Several Opportunities to Win an iPod shuffle During this Panel Discussion . . . Don't Miss Out!
		Charles Baecker, Administrative Director, The Don Beall Center for Innovation & Entrepreneurship, The Paul Merage School of Business. UC Irvine. Bio: 1997- Present: TOSHIBA 2000-Present: Vice President, Strategy & Business Development, responsible for corporate strategy, business planning, and new business development across divisions of Toshiba America Information Systems (computer, telecommunications, imaging, and storage businesses). Also holds position of company spokesperson, with responsibilities related to brand management, corporate public relations and environmental matters, as well as Chief Corporate Social Responsibility Officer, and Chief Environmental Promotion Officer. 1997-2000: Vice President, Business Planning, telecommunications systems business, responsible for launching new business and forming strategic alliances in the telecommunications sector. 1979 – 1997: AT&T 1990-1997: AT&T Business Divisions: Director responsible for new business concepts and strategic planning across business and consumer markets. Public relations head with responsibilities that included speechwriting and development of testimony on government matters for top AT&T executives. Product manager of AT&T’s first commercial electronic mail service. Worked on national technology policy issues (A National Technology Agenda); created strategy statement of the National Advisory Committee on Semiconductors. Produced business plan for advanced satellite communications system. 1979- 1990: Bell Laboratories: Member of Technical Staff, Supervisor and Department Head responsible, at different times, for system engineering of large data networks, mathematical modeling of computer systems, and transition of mainframe applications to distributed PC network, system testing and overall operational planning. Held position of Intellectual Property Adjutant for Bell Lab’s patent portfolio; patent holder. Educational, Community and Personal Bachelor of Science, City University of New York (dual major, Mathematic and Physics,1970); Master of Science, City University of New York (Mathematics, 1976); Master of Arts and Science (New York University, Physics, 1978); Master of Philosophy, New York University (Physics, 1980). Additional: Completed Masters Program in Computer Science (New York University and Bell Labs in-House courses); International Business Program (INSEAD, France); Government Program (Brookings Institution, Washington, D.C.). Member of Orange County Business Council’s Board of Directors and Executive Committee, chairing Workforce Development Committee; Vice-Chair , Orange County Innovation; member Advisory Committee, Chapman University Extended Education; Chair, Beall Center Leadership Council (UCI). Taught mathematics (City University of New York and Syracuse University); co-author, Differential Equation Problem Solver. Former tournament chess player (captain of Bell Labs Chess team). Married, living in Mission Viejo, California.
		Charles Baecker, Administrative Director, The Don Beall Center for Innovation & Entrepreneurship, The Paul Merage School of Business. UC Irvine. Bio: TBD.
		Mark Nielsen, Managing Director of Capistrano Ventures. Panelist Mark Nielsen is a 24-year veteran of the software and wireless industries and has run software companies for the past 19 years. He is the CEO of Wireless21, Inc.; a consulting company focused on business development and advisory services to a wide range of companies. Mr. Nielsen is also a Managing Director of Capistrano Ventures, a company focused on helping companies achieve optimal performance and liquidity events (www.capistranoventures.com). He sits on the boards of three private companies, including being Chairman of Corent Technology (www.corenttech.com) and ISD Corporation (www.isd-corp.com). Mr. Nielsen most recently completed the turnaround of a private software company serving the justice community as interim CEO. In three years, he increased revenues threefold, returned the company to profitability and reduced liabilities by over $2 million. Previously, he has been CEO of both private and public software companies, raising over $25 million in capital. One of his companies was named by Deloitte as a “Fast 50” in Orange County. Mr. Nielsen has been involved in numerous mergers & acquisitions, both as the acquirer and as the acquiree. He has also served on the board or advisory boards of a number of companies focused on various wireless, network management, software and Internet-based opportunities. Mr. Nielsen also serves on the San Juan Capistrano City Council, where he was elected in November, 2006. In his capacity on the Council, he also serves as Mayor Pro Tem, Chairman of the City’s Redevelopment Agency and Chairman of the Open Space Committee. A native of Chicago, Mr. Nielsen received a Bachelor's degree in Communications Studies and Philosophy from Northwestern University. He has served on the Executive Advisory Council of the International Engineering Consortium as well as on the National Board of Directors of the AeA (formerly the American Electronics Association), and is the past Chairman of AeA's Orange County Council. Mr. Nielsen also serves on the Board and Executive Committee of Opera Pacific, the South Coast Medical Center Foundation Board and is a lifetime member of the San Juan Capistrano Historical Society. He has lectured worldwide at trade shows, as well as various business and investor conferences. Mr. Nielsen is also active in the Southern California investment community as a Tech Coast Angel, a member of Ventana Capital’s Executive Advisory Board, and a founding partner of Venture Farm where he sits on the Deal Review Committee. He resides in San Juan Capistrano, CA with his wife and two children.
		R. Scott Feldmann, Partner. IP Attorney (hardware & Software), Crowell & Moring. Panelist M. Scott Feldmann's practice is devoted to intellectual property, especially applied within the context of content, software, computers and the Internet. He has litigated cases involving rights to Digital Signal Processing communications chips, RISC chips, MPEG technology and complex software programs. He has successfully obtained temporary restraining orders in both federal and state court on matters involving copyright infringement, misappropriation of trade secrets, trademark infringement, trade libel, breach of fiduciary duty and unfair competition. He has tried patent, trademark, right of publicity and commercial dispute cases. Mr. Feldmann was previously a management consultant with A.T. Kearney, Inc., advising Fortune 500 companies on strategic investments. Mr. Feldmann was also a Captain in the U.S. Air Force, where he was a test director of "Top Secret-Eyes Only" electronic warfare and "Star Wars" programs. He was awarded the Commendation Medal, and Achievement Medal with oak leaf cluster.
	6:45 – 7:45	(TBA)

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