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The 14th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 October 19 & 20, 2016

University of California, Irvine (UCI) - Calit2

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4th International System-on-Chip (SoC) Conference & exhibit

Conference Program Agenda*


Day One - Wednesday

November 1


Company or University

    7:00 am - 5:00  pm Registration Open All Day  
    8:00 am - 08:15 am Welcome, Opening Remarks, and Conference Updates. Farhad Mafie, President and CEO


    8:15 am - 12:00 pm

New CPU and DSP Cores for Complex SoC Applications

Track Chairman: Shay Gal-On, EEMBC Director of Software Engineering & Leader of EEMBC Technology Center  

    The CA1024: SoC with Integral Parallel Architecture for HDTV Processing, Dr. Gheorghe Stefan, Chief Scientist & co-Founder.

Connex Technology


Mike Butts, Architect, Implementing A New, Massively-Parallel, MIMD Computing Fabric SoC



Delivering Data Engine Benefits in the System Context, Steve Steele, Director of Data Engines Division, Business Development



9:45 am - 10:00 am

Morning Coffee Break

  10:00 am - 10:30 am

Keynote Speech: Advances in Packaging, CMOS Design and Flexible Architectures for New Ultra-Mobile PC (UMPC).  Dr. Dominik Schmidt, Architect, and Arup Gupta, Director, Wireless Platform Technology at Mobility Group



Nanometer MPSoC Design Using Configured Cores. Steve Leibson, Technology Evangelist



Dual-Cores SoC Simplifies Digital Video Systems, Dr. Thanh Tran, Senior Member Technical Staff.

Texas Instruments

    Hitting the Sweet Spot Between Hard Wired Logic and Programmable DSPs With HiveFlex Processors for New SoC Applications. George Szanto, Vice President of Marketing

Silicon Hive

    12:00 pm - 1:00 pm


    1:00 pm - 1:30 pm Keynote Speech: From 5000nm to 45nm: A 30 Year Journey in Chip Design
Low Power Challenges in System-on-a-Chip Design.  Dr. Mehdi Hatamian, Vice President of Engineering, DSP Microelectronics


    1:30 pm - 3:00 pm

Memory sub-system Advances and Trends

Track Chairman: Dr. Raman Menon Unnikrishnan. Dean of the College of Engineering and Computer Science, California State University, Fullerton 

  1:30 pm - 2:00 pm

Keynote Speech: Toward Low-Power and High-Speed Memory-Based Computing Chips. Dr. Tadao Nakamura, Professor of Computer Science Tohoku University, Japan. Laureate of IEEE Taylor L. Booth Award IEEE Fellow. 

Tohoku University Japan


Osmium Packaging Technology. Kyle Kirby, Engineering Manager --The 3D Stacking Development Team.

Micron Technology


How to Cut Die Cost in Half.  Dr. Pierre Fazan, Founder and CTO.

Innovative Silicon

    3:00 pm - 3:15 pm Afternoon Coffee Break  
    3:15 pm - 5:15 pm

Network-on-Chip (NoC) Architectures for Complex SoCs

Track Chairman: Dr. Goran Matijasevic, Director of Research Development, The Henry Samueli School of Engineering, University of California, Irvine

    Exploiting Interconnect-Centric Structural Regularity for Cost-Efficient SoC Design. Marcello Coppola

ST Microelectronics

    "Abstraction Levels for SoC Memory Subsystem Design with MemMax. Jeff Haight, Director Technical Marketing & Zainab Al-Shamma, Field Applications Engineer.



Design and Analysis of A Network-on-Chip (NoC) Processor Architecture.  Dr. Nader Bagherzadeh

University of California, Irvine


Communication Analysis of the Cell Broadband Engine Processor. Dr. Fabrizio Petrini.

Pacific Northwest National Laboratory


  5:15 pm - 6:15 pm


Panel: Architectural and Performance-Related Challenges for Complex SoCs  

Moderator: Ron Wilson, Executive Editor, EDN Worldwide.


1. Dr. Marco Racanelli, Vice President of Technology and Engineering, Jazz Semiconductor.

2. Larry Morrell, Vice President of IP Products, Impinj Inc.

3. David Fritz, Chief Executive Officer, Silistix, Inc.

4. Bill Chown, Director of Engineering, Mentor Graphics. Representing The SPIRIT Consortium.

5. Paolo Cocchiglia, Vice President, ADS (ASIC Design and Security) Infineon Technologies North America Corp.



4:30 pm - 8:30 pm

Conference Exhibit & Reception Open


Day Two - Thursday

November 2


Company or University

    7:00 am - 5:00  pm Registration Open  
    8:00 am - 8:15 am Welcome and Opening Remarks, Technology/Market Trends. Farhad Mafie, President and CEO


    8:15 am - 12:00 pm

Semiconductor Trends and New Design Approaches for Complex SoCs

Track Chairman: Farhad Mafie, Savant Company Inc.


HardCopy Structured ASICs A Superior Design Flow, Francis Chow, Business Development Manager.



Pre-Mature Claims to Structured ASIC Demise, Rick Mosher, IP Product Manager
Structured Digital Products.

AMI Semiconductor

    Low Power SoC Design Using Multiple Voltage Islands and Adaptive Voltage Scaling. Gordon Mortensen, Engineering Director - Advanced Power

National Semiconductor


  9:45 am - 10:00 am

Morning Coffee Break  
    10:00 am - 12:00 pm

Keynote Speech: Lessons learned at 65nm that will be applied to 45nm. Ana Molnar Hunter, Vice President of Technology 


CMOS, Scaling, and the Future CMOS Scaling. Has it bottomed out? Ray Abrishami, Senior Director of Wireless Business Group

Fujitsu Microelectronics

Ultra Low-Power Memory IPs for SoC Designs.  Dr. Cyrus Afghahi, CEO and Co-Founder.



SerDes Modeling Challenges in complex SoC and Solutions using IBISv4.1, Syed B. Huq, Senior Hardware Engineering Manager.


    12:00 pm - 1:00 pm Lunch  
    1:00 pm - 1:30 pm

Keynote Speech: Avoiding the Death of The SoC Venture, A New Player is Born. Dr. Juan-Antonio Carballo, Venture Strategy Executive.


    1:30 pm - 5:15 pm

EDA Tools and Design Methodologies for Complex SoCs

 Track Chairman: Dave Bursky, Semiconductor Editor, EETimes Magazine

    The Quiet Revolution. Steve Carlson, Vice President.

Cadence Design Systems


What’s Up? Growth Areas in the Electronics Industry.  John Gallagher, Senior Director ASIC Synthesis Marketing


    High-level to RTL Equivalence and Model Checking of High-Level Designs.  Dr. Carl Pixley


    3:00 pm - 3:15 pm Afternoon Coffee Break  
    Innovations in Yield Learning, Dr. Stephen Pateras, Senior Director.


    C-RTL Equivalence Checking: The bridge between ESL and RTL, Dr. Gagan Hasteer, Vice President of Engineering and Co-Founder.


    Chip Instrumentation Solutions for SoC Analysis. Dr. Neal Stollon, Director of Technical Marketing.

First Silicon Solutions

    Future direction of virtual system prototyping, Dr. Rob Bedichek, Vice President of Engineering.

VaST Systems Technology

    5:15 pm - 6:15 pm


Panel: EDA Challenges for Complex SoC and ASIC Designs

Moderator: Dave Bursky, Semiconductor Editor, EETimes Magazine



1. Jerry Frenkil, CTO, VP and General Manager, Silicon Business Unit Sequence Design.

2. Max Lloyd, President and CEO, ViASIC

3. Robert Jones, Sr. Director, Custom Design Business Unit, Magma Design Automation

4. AK Kalekos, Vice President of Marketing and Business Development, CoWare.

5. Dr. Adriaan Ligtenberg, President, CEO and co-founder of Takumi Technology.



* Program is subject to change.  Savant Company Inc. reserves the right to revise or modify the above program at its sole discretion.


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Copyright © 2006 by Savant Company Inc. All rights reserved. 






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