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Day One -
Wednesday
November 1 |
Session |
Company or University |
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7:00 am - 5:00 pm |
Registration Open All Day |
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8:00 am - 08:15 am |
Welcome, Opening Remarks, and Conference Updates. Farhad Mafie, President
and CEO |
Savant |
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8:15 am - 12:00 pm |
New CPU and DSP Cores for
Complex SoC
Applications
Track Chairman:
Shay Gal-On, EEMBC Director
of Software Engineering & Leader of EEMBC Technology Center
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The CA1024: SoC with Integral Parallel Architecture for HDTV Processing, Dr. Gheorghe
Stefan, Chief Scientist & co-Founder. |
Connex Technology |
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Mike
Butts, Architect, Implementing A New, Massively-Parallel, MIMD Computing Fabric
SoC |
Ambric |
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Delivering
Data Engine Benefits in the System Context, Steve
Steele, Director of Data Engines Division, Business Development |
ARM |
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9:45 am - 10:00 am |
Morning Coffee Break |
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10:00 am - 10:30 am |
Keynote Speech: Advances
in Packaging, CMOS Design and Flexible Architectures for New Ultra-Mobile PC
(UMPC). Dr. Dominik Schmidt,
Architect, and
Arup Gupta, Director, Wireless Platform Technology at Mobility Group
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Intel |
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Nanometer
MPSoC Design Using Configured Cores.
Steve Leibson, Technology Evangelist |
Tensilica |
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Dual-Cores SoC Simplifies Digital Video Systems, Dr. Thanh Tran, Senior Member Technical Staff. |
Texas Instruments |
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Hitting
the Sweet Spot Between Hard Wired Logic and Programmable DSPs With HiveFlex
Processors for New SoC Applications. George Szanto, Vice President of Marketing |
Silicon Hive |
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12:00 pm - 1:00 pm
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Lunch
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1:00 pm - 1:30 pm |
Keynote Speech: From 5000nm to 45nm: A 30 Year Journey in Chip Design
Low Power Challenges in System-on-a-Chip Design. Dr. Mehdi Hatamian, Vice President of Engineering,
DSP Microelectronics |
Broadcom |
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1:30 pm - 3:00 pm |
Memory sub-system Advances and Trends
Track Chairman:
Dr. Raman Menon Unnikrishnan. Dean
of the College of Engineering and Computer Science, California State
University, Fullerton
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1:30 pm - 2:00 pm |
Keynote Speech:
Toward
Low-Power and High-Speed Memory-Based Computing Chips. Dr. Tadao Nakamura,
Professor of Computer Science Tohoku University, Japan. Laureate of IEEE
Taylor L. Booth Award IEEE Fellow. |
Tohoku
University Japan |
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Osmium Packaging Technology. Kyle Kirby, Engineering Manager --The 3D
Stacking Development Team. |
Micron
Technology |
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How to
Cut Die Cost in Half. Dr. Pierre Fazan, Founder and CTO. |
Innovative
Silicon |
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3:00
pm - 3:15 pm |
Afternoon
Coffee Break |
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3:15 pm - 5:15 pm |
Network-on-Chip (NoC) Architectures for Complex SoCs
Track Chairman: Dr. Goran
Matijasevic, Director of Research Development, The Henry Samueli School of
Engineering, University of California, Irvine
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Exploiting
Interconnect-Centric Structural Regularity for Cost-Efficient SoC Design.
Marcello Coppola |
ST Microelectronics |
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"Abstraction Levels for SoC Memory Subsystem Design with MemMax.
Jeff
Haight, Director Technical Marketing & Zainab Al-Shamma, Field
Applications Engineer.
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SONICS Inc. |
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Design
and Analysis of A Network-on-Chip (NoC) Processor Architecture.
Dr.
Nader Bagherzadeh |
University of California,
Irvine |
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Communication Analysis of the Cell Broadband Engine Processor. Dr. Fabrizio
Petrini. |
Pacific Northwest National
Laboratory |
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5:15 pm - 6:15 pm
Panel |
Panel: Architectural and Performance-Related Challenges for Complex SoCs
Moderator:
Ron
Wilson, Executive Editor, EDN Worldwide.
Panelists:
1.
Dr. Marco
Racanelli, Vice President of Technology and Engineering, Jazz Semiconductor.
2. Larry Morrell, Vice
President of IP Products, Impinj Inc.
3.
David Fritz, Chief Executive
Officer, Silistix, Inc.
4. Bill Chown, Director of Engineering, Mentor Graphics. Representing The SPIRIT
Consortium.
5. Paolo Cocchiglia, Vice
President, ADS (ASIC Design and Security) Infineon Technologies North
America Corp.
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4:30 pm - 8:30 pm
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Conference Exhibit
& Reception Open
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Day Two - Thursday
November 2 |
Session |
Company or University |
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7:00 am - 5:00 pm |
Registration Open |
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8:00 am - 8:15 am |
Welcome and Opening Remarks, Technology/Market Trends. Farhad Mafie,
President and CEO |
Savant |
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8:15 am - 12:00 pm |
Semiconductor
Trends and New Design Approaches for Complex SoCs
Track Chairman: Farhad Mafie,
Savant Company Inc. |
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HardCopy Structured ASICs A
Superior Design Flow,
Francis Chow, Business Development Manager.
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Altera |
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Pre-Mature Claims to Structured ASIC Demise, Rick Mosher, IP Product Manager
Structured Digital Products.
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AMI Semiconductor |
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Low Power SoC Design Using Multiple Voltage Islands and
Adaptive Voltage Scaling. Gordon
Mortensen, Engineering Director - Advanced Power |
National Semiconductor |
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9:45 am - 10:00 am |
Morning Coffee Break |
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10:00 am - 12:00 pm |
Keynote Speech: Lessons learned at 65nm that will be applied to 45nm.
Ana Molnar Hunter, Vice
President of Technology |
Samsung |
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CMOS, Scaling, and the Future CMOS Scaling. Has it bottomed
out? Ray
Abrishami, Senior Director of Wireless Business Group
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Fujitsu Microelectronics |
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Ultra
Low-Power Memory IPs for SoC Designs. Dr. Cyrus Afghahi, CEO and
Co-Founder.
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Novelics |
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SerDes
Modeling Challenges in complex SoC and Solutions using IBISv4.1, Syed B.
Huq, Senior Hardware Engineering Manager.
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Cisco |
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12:00 pm - 1:00 pm |
Lunch |
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1:00 pm - 1:30 pm |
Keynote Speech: Avoiding the Death of The SoC Venture, A New Player is
Born. Dr. Juan-Antonio Carballo,
Venture Strategy Executive. |
IBM |
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1:30 pm - 5:15 pm |
EDA Tools and
Design Methodologies for Complex SoCs
Track
Chairman: Dave Bursky, Semiconductor Editor, EETimes Magazine |
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The Quiet Revolution.
Steve Carlson,
Vice President. |
Cadence Design Systems
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What’s Up? Growth Areas in the
Electronics Industry. John Gallagher, Senior Director ASIC Synthesis
Marketing
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Synplicity |
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High-level
to RTL Equivalence and Model Checking of High-Level Designs.
Dr. Carl Pixley |
Synopsys
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3:00 pm - 3:15 pm |
Afternoon Coffee Break |
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Innovations in Yield Learning,
Dr. Stephen Pateras, Senior Director.
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LogicVision
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C-RTL
Equivalence Checking: The bridge between ESL and RTL, Dr. Gagan Hasteer,
Vice President of Engineering and Co-Founder.
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Calypto
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Chip
Instrumentation Solutions for SoC Analysis. Dr. Neal Stollon, Director of
Technical Marketing. |
First Silicon Solutions
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Future
direction of virtual system prototyping, Dr. Rob Bedichek, Vice President of
Engineering.
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VaST
Systems Technology
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5:15 pm - 6:15 pm
Panel |
Panel: EDA
Challenges for Complex SoC and ASIC Designs
Moderator: Dave Bursky,
Semiconductor Editor, EETimes
Magazine
Panelists:
1.
Jerry
Frenkil, CTO, VP and General Manager, Silicon Business Unit
Sequence Design.
2. Max Lloyd, President and CEO, ViASIC
3.
Robert Jones, Sr. Director, Custom Design Business Unit,
Magma Design Automation
4.
AK Kalekos, Vice President of Marketing and Business Development, CoWare.
5. Dr.
Adriaan Ligtenberg, President, CEO and co-founder of Takumi Technology.
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