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To present and/or exhibit at this
highly-targeted International System-on-Chip (SoC) Conference, please contact:
949-981-1837 or SoC.Conf.Update@Gmail.com |
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Directions &
Parking for Calit2 Building at the University of California, Irvine (UCI)
Click Here To
Download The UCI Campus Map
Directions &
Parking for Calit2 Building at the University of California, Irvine (UCI)
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Schedule & Program Summary
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SoC Conference Day 1 |
Wednesday, October 21, 2015
UCI - Calit2 Building |
8:00 am - 7:00 pm |
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SoC Conference Day 2 |
Thursday, October 22, 2015
UCI - Calit2 Building |
8:00 am - 7:00 pm |
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SoC Tabletop Exhibit &
Reception |
Wednesday, October 21, 2015
UCI - Calit2 Building |
2:00 pm - 7:00 pm |
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Microsemi
Keynote
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Jim
Aralis, Chief Technology Officer (CTO), and Vice President of R&D.
Abstract: This
presentation will outline the new process, processor, and packaging
technologies that are enabling the expansion of mixed-signal SoC product
development efforts. Subjects that will be covered include the optimization
of design methodologies, mode partitioning, and process selection to
maximize cost-savings, performance, and time-to-market. The presenter will
also discuss how expertise in analog processing, signal conditioning,
precision timing, and high speed wired and wireless communications design
remain critical for designing differentiated products in an expanding and
evolving digital environment.
Bio: Jim Aralis has served as
chief technology officer and vice president of R&D for Microsemi since
January 2007. He has more than 30 years experience in developing custom
analog device and process technologies, analog and mixed-signal ICs and
systems, and CAD systems. Jim played a key role in transitioning Microsemi to a virtually fabless
model, supporting multiple process technologies including, high voltage and
high power BCD/CMOS, high power high integration CMOS, GaAs, SiGe, IPD, RF
CMOS SoI, GaN, SiC, and several high-density packaging technologies.
From 2000 to 2007, Jim established and served as senior design director of
Maxim Integrated Product’s engineering center in Irvine, Calif. Before that,
he spent 7 years with Texas Instruments/ Silicon Systems as mixed-signal
design head and senior principal engineer. Additional experience includes 11
years with Hughes Aircraft Company in positions of increasing responsibility
including senior scientist. Jim earned a bachelor of science degree in
Math Applied Science and Physics and a master of science in electrical
engineering from UCLA. He holds 9 patents for circuit and system design.
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University of California,
Irvine
Keynote
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Dr.
G.P. Li, Cali2 Director, University of California, Irvine, Professor of
Engineering.
Abstract: TBA.
Bio: Dr. Li is a professor at
the University of California, Irvine, with appointments in three
departments: Electrical Engineering and Computer Science, Chemical
Engineering and Materials Science, and Biomedical Engineering. At UCI, he
also serves as Calit2 division director and director of the Integrated
Nanosystems Research Facility in The Henry Samueli School of Engineering.
Dr. Li holds 18 U.S. patents, has 15 patents pending and has published more
than 280 research papers involving microelectronic technologies, microwave
circuit design, Micro-Electro-Mechanical Systems (MEMS) for communication
and biomedical instrumentation applications, and bio-nano-IT technology. He
received his bachelor’s degree in electrical engineering from National Cheng
Kung University (NCKU) in Taiwan, and his master’s and doctorate degrees,
also in electrical engineering, from UCLA. During his tenure as
a research staff member and manager of the technology group at IBM’s T. J.
Watson Research Center (1983-1988), Li worked in the area of VLSI technology
and led a research/development team to transfer the technology into the
marketplace. In 1987, he chaired a committee charged with defining IBM’s
semiconductor technology roadmap beyond the year 2000. A member of
numerous technical committees at professional conferences, Li was chair of
the Taiwan VLSI Technology, Circuit, and System Conference in 2006. He also
served as chair of the executive committee for electronics manufacturing
research and new materials at the University of California. Dr. Li received
an outstanding research contribution award from IBM (1987), two outstanding
engineering professor awards from UCI (1997 and 2001), the UCI Innovators
Award (2005), best paper award from the ITC International Telemetering
Conference (2005), and outstanding Asian American and Pacific Islander
Community Leaders and Role Models award by the Asian Business Association of
Orange County (2009). Li has been involved in several startup
companies as a co-founder or member of the technical advisory board.
Currently, he directs TechPortal, a technology business incubator housed at
the UCI division of Calit2, which supports and nurtures young companies and
university researchers commercializing their technologies. His current
research interests focus on developing technologies for efficient energy
utilization and consumption, and e-health.
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Intel
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Dr.
Jeff Parkhurst, Intel Science & Technology Center Program Director
Cloud Computing and Big Data.
Big Data -- Hope or Hype
Abstract: Big Data is becoming more prevalent in our daily conversation.
Mining and processing it holds the hope of providing insight into areas that
a few years ago would have been considered out of reach. Efficient
transportation for big cities, retail and genomics are all being studied
with renewed vigor. However, the promise of Big Data is also tempered by the
potential to misuse and misinterpret. This talk will look at both the
potential and the problems in working in with large amounts of data and will
take a peak into the research at the Intel Science and Technology center for
Big Data.
Bio: Dr. Jeff Parkhurst is the Program Director for three Intel Science and
Technology Centers focusing on Embedded Computing, Cloud Computing and Big
Data. He is responsible for managing the operational details in each center
as well as aiding in direction setting of the research. The Program Director
is the primary liaison between Intel and the universities on all operational
matters including contracts, IP, space, logistics, funding, and
technology/knowledge transfer. Prior to this assignment, Jeff was an
Academic Research Programs Manager working with senior technologists
internal and external to Intel setting research directions for the design
science areas of the Semiconductor Research Corporation (SRC). Jeff received
his BS from University of Nevada at Reno in 1983 and his MS from the
University of California at Davis in 1988 and his PhD at Purdue University
in 1994. Dr. Parkhurst is the author of numerous papers and one patent.
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Skyworks Solutions, Inc.
Keynote
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James P. Young Vice
President, Advanced Development, Skyworks Solutions, Inc.
Keynote: "Mobile Front End Module The Battle Between SIP & SoC."
Bio: James P. Young is vice
president of advanced development at Skyworks Solutions, Inc. where he is
responsible for mobile handset power amplifier and front end module design.
His expertise includes power amplifier and RFIC circuit and system design in
CMOS, SOI, BiCMOS, bipolar, and GaAs technologies. James holds 18 patents,
has authored or co-authored over 22 papers, and taught several short courses
mainly on RFIC design. He holds a bachelor’s of science in electrical
engineering from Rose-Hulman Institute of Technology in Terra Haute,
Indiana.
Abstract: Ubiquitous
demand for mobile platforms with extended talk times and high-speed data is
creating an unprecedented level of analog and RF complexity. As the wireless
market transitions from 3G to 4G standards such as LTE and LTE-A, front-end
architectural challenges are being compounded by demanding coexistence,
shielding and harmonic requirements above and beyond the traditional
constraints of power efficiency, size and cost. Front-end solutions will
soon have to support up to 50 frequency bands and 100 carrier aggregation
combinations. Next-generation products will also support LTE in WiFi, GPS,
Bluetooth®, Mobile TV, NFC and other non-cellular services.
While higher peak to average modulations are driving significant innovation
in power added efficiency in the basic transistor characteristics, and
system level approaches including DPD, APT and envelope tracking when
combined can reduce power consumption by up to 30 percent, GaAs HBT
technology and roadmap maintains a 10 percent efficiency advantage over SOI
and CMOS. Another critical technology for system level efficiency is antenna
tuning, where switches can be applied for both on-antenna aperture tuning as
well as the antenna-feed impedance tuning.
Both system-in-package and system-on-chip approaches are being pursued to
integrate all of the RF and analog content between the transceiver and
antenna, including multiband power amplifiers, high throw switches,
filtering, duplexing and controls. System-in-package solutions such as
Skyworks’ SkyOne™ family of products use multiple technologies to optimize
the performance, size and cost of each functional block and provide a fully
shielded and packaged solution to address co-existence and interference as
the size of the RF board continues to shrink. |
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