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The 14th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 October 19 & 20, 2016

University of California, Irvine (UCI) - Calit2

13th International SoC Conference In Pictures. . .

         
 
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8th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 

November 3 & 4, 2010

Hilton Irvine/Orange County Airport, Southern California

 

The Most Informative & Targeted

SoC, ASIC, FPGA, ASSP, and Foundry Technology Conference & Exhibit of the Year

 

Don't Miss Out!

 

If your organization is interested in participating in this highly informative and recognized Conference, please contact us via the following emails or phone numbers:

SoC@SoCconference.com  or  949-851-1714
 

 

Workshop by Mentor Graphics

 Effective Debug of Processor-based RTL SoC Simulations.

 
   

Day: Thursday, Nov 4, 2010.

Time: 2:00 p.m. 4:45 p.m.

Location: Conference Room A, SoC Conference, Hilton Irvine.

To Register, Please contact SoC@SoCconference.com

 
 

 

In this workshop you will learn how to accelerate the diagnostic and debug phase of your processor-based design using processor-driven tests. If you are running processor-driven tests in digital simulation on your processor-based design, you know how difficult and time consuming it is to figure out what went wrong in a failing simulation. Manually slogging through log.EIS or other processor trace files, assembly listings, symbol tables, and logic simulation waveforms is slow and very inefficient. This workshop will describe ways to provide processor debug views for source/assembly, registers, memories, variables, etc. that are completely synchronized with the logic simulator waveforms. It will describe how you can run simulation, and then in post-simulation, you can step forward and backward through the simulation in a matter of seconds. Codelink connects to either the ARM, MIPS, or IBM PowerPC processor in design signoff model, RTL, or gate form instantiated in a block or chip-level simulation and requires no change to the design or processor models.

 
       
  This Workshop has been cancelled. It will be offered very soon. Digital TV on a Chip – An Overview
By Dr. Jordan Isailovic, President, JRI Technology. Savant Affiliate.
 
  Workshop by JRI Technology

Day: Thursday, Nov 4, 2010.

Time: 2:00 p.m. 4:45 p.m.

Location: Conference Room B, SoC Conference, Hilton Irvine.

To Register, Please contact SoC@SoCconference.com

 
   

DTV’s rapid growth in popularity is spurred by the high-definition video quality as well as the availability of a variety of new features and services including video on demand (VoD), gaming, security, PVR, interactive TV, merchandising and Web browser capabilities. In this half-day Workshop, an overview of Digital TV technology and its system-level block diagram will be provided and main blocks will be discussed. Dr. Jordan Isailovic, will covers the video chain from the initial capture of video content to the final viewing experience. Applicable compression technologies such as MPEG will be reviewed. Topics that will be reviewed, include:

  • Digital Television architecture and functionality

  • MPEG TV

  • System Interfaces

  • Major video processing building blocks

  • Strategic consideration for the design of digital TV system-on-chip
    Trade-off between performance and cost.

  • Multi-format picture decoding in support of high definition AVC, H.264, VC-1, AVS and MPEG-2 streams.

  • Aspect ratio conversions; AFD, closed captions 608/708

  • Synchronization in the MPEG world; Lip-sync and latency issues
    Conditional access, authorization and control

  • Major trends and Future A/V Standards, H.265, etc.

  • Looking beyond HD: 3D, Hi-vision, mobile TV, etc.

Who Should Attend:
Engineers, technical management, system architects, technology analysts, systems developers and integrators, etc., who are interested in getting a comprehensive overview of the Digital TV technology and its single chip opportunity would greatly benefit from this half-day informative workshop.


Instructor: Dr. Jordan Isailovic is a Professor of Electrical Engineering at California State University. He is the author of Videodisc and Optical Memory Technologies and Videodisc Systems: Theory and Applications. He has authored numerous technical articles and holds several patents on digital information storage techniques and video signal processing. He presented the world's first public engineering course on videodisc technology (January 1982) and taught the world's first graduate courses on videodisc and optical memories (CD, CD-ROM, etc.). For more details about Dr. Isailovic.

 
       

 

 

 

 

 

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