8th International SoC Conference


		Day One Nov. 3, 2010 SoC Conference Program Agenda*
	Savant Company Inc.	Farhad Mafie, SoC Conference Chairman, President and CEO of Savant Company Inc. "Welcome and Opening Remarks, Technology/Market Trends." Farhad Mafie is President and CEO of Savant Company Inc., a technology marketing company in Irvine, CA. Savant specializes in marketing and sales of semiconductor IC/IP products, SoC/ASIC services and solutions, as well as providing targeted technical- and business-related training seminars and conferences globally. He has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. He is the former Vice President of Marketing and Engineering at Toshiba Semiconductor. He has also worked in strategic marketing, project and design engineering at Lucent Technologies, Unisys, and MSI Data. Farhad has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. He is an author and a translator, and his articles have been published in a variety of journals and Web-based magazines on technology and political affairs. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units. Farhad is an active member of IEEE, and he is the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN). He is also a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs.
		More than Moore: Emerging Trends & Challenges in Integration of RF & Analog/Mixed-Signal (RF-AMS) Content into Low-Power SoC Platforms. Track Chairman: Dr. Michael Green, Professor & Chair Department of Electrical & Computer Engineering, UC Irvine.
	S3 Group	Cormac O’Sullivan, RF & Mixed Signal Engineering Team Lead. RF SoC Development Flow. Abstract: In this presentation the background and market conditions driving the increasing integration of analog and mixed signal content will be briefly discussed. Featuring a case study of a recent RF SoC completed by S3 Group, the system cost benefits that can be achieved with aggressive integration of high performance RF, analog, mixed-signal and digital content, will be outlined. S3 Group’s accelerator platform leveraging proprietary system design tools, RF building blocks, mixed-signal IP and a pre-built mixed-mode verification environment to accelerate developments will be described. The tangible benefits of each facet of our Mixed Signal SoC accelerator platform will be highlighted showing how it leads to lower risk and reduced cost integration programs. Finally a new paradigm for RF SoCs - an integration roadmap which accelerates time to market, balances risk and investment, while achieving the optimal system partition as product volume moves from proof of concept prototype to mass production – will be introduced. Bio: Cormac E. O’Sullivan received the B.E. degree in electronic engineering from University College Cork (U.C.C.), Cork, Ireland, in 2001. He joined the RF Group, Analog Devices, Ireland, in the same year as an RF Design Engineer. There he was involved in the design of integrated RF transceivers and transmitters in deep-submicron CMOS technologies. He has patented advanced technology in the area of RF transmitter design and PLLs. His technical interests are in the ﬁeld of low-power analog CMOS circuits, RF IC, and RF system design. He joined S3 Group Consumer Silicon, Cork, in 2006 where he has lead a team developing highly integrated RF SoCs for standards based and proprietary systems.
	UC Irvine	Dr. Payam Heydari, Professor, Electrical Engineering and Computer Science. UC Irvine. Fully Integrated Passive Imaging in Silicon Technologies. Abstract: Millimeter-wave (MMW) radiometer has been around since 1960’s. Nevertheless, only recently, real-time MMW imaging techniques have become increasingly more attractive to military and public as a result of rapid progress in monolithic MMW integrated circuit technologies. Applications of MMW imaging include remote sensing, security surveillance and nondestructive inspection for medical and environment field. Compared to traditional optical imaging technology, MMW imaging can be used not only in clear weather but also in low-visibility conditions such as fogs, and even through clothing. Passive MMW (PMMW) imaging is specifically attractive because its detection of emitted thermal radiation from a scene reduces public health concerns for medical applications and security concerns for military applications. In order to generate real-time images, the integration time of the imager should not be greater than about 10-25ms. Current imaging systems using mechanical scanning employ high-performance low-noise receivers implemented in III-V compound semiconductor technologies with low-level of integration. Silicon technology, with its superior integration capability and lower cost in high volumes, is poised to be the ultimate solution for a fully integrated PMMW imaging system. Our research group at UC Irvine has developed a single-chip highly-integrated MMW imaging receiver (RX) operating in the W band, fully utilizing the high level of integration that silicon offers. The goal of this work is to demonstrate the potential of silicon chips as a lower cost alternative to III-V-based imaging chip-sets. This talk will give an overview of the millimeter-wave imaging project in Nanoscale Communication Integrated Circuits (NCIC) Labs at UC-Irvine. Bio: Dr. Payam Heydari received the B.S. and M.S. degrees (with honors) in electrical engineering from the Sharif University of Technology, Tehran, Iran, in 1992 and 1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California, Los Angeles, in 2001. He is currently a Professor at the department of electrical engineering and computer science at the UC Irvine. He is also the director of the Nanoscale Communication IC Lab, where he has led graduate students to tape-out over 25 integrated circuits that have resulted in more than 70 journal and conference publications, one book, and several patents. Dr. Heydari is also the cofounder of ZeroWatt Technologies and is the recipient of several awards, including: the 2007 IEEE Circuits and Systems Society Guillemin-Cauer Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 National Science Foundation (NSF) CAREER Award, and much more.
	Intel	Dr. Jeff Parkhurst, Academic Research Programs Manager in the Design Sciences Area. Delivering cost effective SoC based platform solutions: Design and Test challenges in the More than Moore environment. Abstract: For more than 30 years, Intel has been on a path of decreasing transistor feature size and increasing density exponentially. As Intel expands its business into the SoC world, new challenges emerge. We are not just integrating RF, AMS components with digital, but are also trying to address issues at the platform level expanding into the software/firmware domain. This talk will discuss the unique challenges in the design and test area that we face and barriers we need to overcome to be successful in the SoC space. Bio: Jeff Parkhurst received his PhD from Purdue University in 1994. He has worked as a circuits designer on a variety of projects. He is currently academic research programs manager for design sciences at Intel Corp.
	UC Irvine	Dr. Michael Green, Professor & Chair Department of Electrical & Computer Engineering. Novel CMOS Design Techniques for Multi-Gb/s Broadband Communication Circuits. Abstract: The use of optical fibers for broadband communication has dramatically reduced the speed bottleneck in wide-area networks (WANs). Indeed, the bandwidth capability of state-of-the art optical fibers is so large that it is the electrical components connected at the ends of the fibers that limit transmission speeds. Multi-gigibit communications IC's, until recently dominated by very fast, expensive processes (e.g., III-V devices), are now commonly being designed using standard CMOS technologies. The advantages of higher integration levels and lower power dissipation are strong motivations for moving to CMOS; however, designers are confronted with additional challenges of high-speed design with devices that exhibit lower gain & bandwidth and higher noise as compared to other technologies. Some novel design techniques that enhance the speed and performance of CMOS broadband circuits will be presented, including: Supply-insensitive ring oscillators; novel clock divider techniques; design of adaptive equalizers for transmission across copper, based on analog and DFE approaches; design of a 40Gb/s transmitter in 180nm CMOS using distributed amplifier design techniques. Bio: Dr. Michael Green received the B.S. degree in electrical engineering from University of California, Berkeley in 1984 and the M.S. and Ph.D. degrees in electrical engineering from University of California, Los Angeles in 1988 and 1991, respectively. He has been on the faculty of the EECS department at University of California, Irvine since 1997 and has been Chair of the department since September 2009. From 1999 to 2001 he was an IC designer with the Optical Transport Group at Broadcom Corp. (formerly Newport Communications) where he was part of a design team that produced the world's first 10 Gigabit-per-second broadband transmitter chip using standard CMOS. His current research interests include the design of analog & mixed-signal integrated circuits for use in high-speed broadband communication networks. Dr. Green was the recipient of the Outstanding Master's Degree Candidate Award in 1989 and the Outstanding Ph.D. Degree Candidate Award in 1991, both from the UCLA School of Engineering and Applied Science. He is also the recipient of the Sigma Xi Prize for Outstanding Graduate Science Student at UCLA in 1991, the 1994 Guillemin-Cauer Award of the IEEE Circuits and Systems Society, the 1994 W. R. G. Baker Award of the IEEE, a 1994 National Young Investigator Award from the National Science Foundation and the Award for New Technical Concepts in Electrical Engineering from IEEE Region 1.
	Netlogic Microsystems Keynote	Dr. Juan-Antonio Carballo, Director, Major Account, Netlogic Microsystems. Keynote Dr. Juan-Antonio Carballo Director of major account at Netlogic. He was the IBM Corporation's Venture Capital Executive for Semiconductors and Hardware Systems, responsible for creating and managing strategic projects with top-tier Venture Capital firms and their portfolio companies. Prior to this role, Juan-Antonio was leading research in adaptive communications chips at IBM Research. He won an IBM Research Division award for his work in this area. He filed 23 patents and has over 20 publications in low-power design, communications systems, design economics, and electronic design management. He is the Chair of the International Technology Roadmap for Semiconductors (ITRS) Design and System Drivers Chapters, the Chair Elect of IEEE's DATC Committee, and VSIA's R&D Chair in 2004-5. He has been on the committee of six symposiums and conferences, and was the General Chair for Electronic Design Processes 2004 in Monterey, CA. His prior work experience includes stays at Digital Equipment (currently HP) and LSI Logic. Juan-Antonio holds a Ph.D. in Electrical Engineering from the University of Michigan, an M.B.A. from the College des Ingenieurs (Paris),and a M.Sc. in Telecommunications Engineering from the Universidad Politecnica de Madrid.
	Lunch	Lunch
		Emerging Technologies, Trends, and Possibilities in Designing Multicore SoC Platforms. Track Chairman: Dr. Payam Heydari, Professor, Electrical Engineering and Computer Science, UC Irvine.
		Panel: "More than Moore: Emerging Trends & Challenges in Integration of RF & Analog/Mixed-Signal (RF-AMS) Content into Low-Power SoC Platforms."
	Panel EDA360 EDN UCLA Berkeley Design Automation, Inc. IC Manage Cypress Semiconductor X-FAB Group Broadcom	Steve Leibson, EDA360 Evangelist. Moderator Bio: Steve Leibson literally wrote the books on IP-based SOC design — “Designing SOCs with Configured Cores,” published in 2006 and “Engineering the Complex SOC,” co-authored with Dr. Chris Rowen and published in 2004. Steve has been evangelizing IP-centric SOC design since 2001 through articles, White Papers, books and book chapters, Webinars, videos, invited keynote presentations, conference presentations, and in-booth trade show presentations around the world. He is now the EDA360 Evangelist and Marketing Director at Cadence Design Systems, a leading EDA vendor specializing in system and chip-level design tools, design IP and IP design platforms, and verification IP. Prior to joining Tensilica as Technology Evangelist, he was VP of Content for Reed-Elsevier/Microdesign Resources, managed and ran the Microprocessor Forum, and he has served as editor in chief of the Microprocessor Report newsletter, EDN Magazine, and Embedded Developer’s journal where he set publication vision and mission and managed editorial and production teams of experienced journalists and writer/engineers. He has many years of experience in persuasively communicating with the electronic design community across a broad range of topics and has made a particular study of reaching the extremely elusive design community for the purpose of lead generation through diverse channels including the Internet, blogs, social media, and online video. Panelists: 1. Professor Sudhakar Pamarti (Research Group: Signal Processing and Circuit Engineering), UCLA. 2. Dr. Ravi Subramanian, President & CEO, Berkeley Design Automation, Inc. 3. Dr. Ted Williams, Director of Silicon IP, IC Manage. 4. Dr. Babak Taheri, Vice President, Technical Staff, in charge of IP and new product development, Cypress Semiconductor. 5. Mr. Olaf Zinke, Product Line Manager AMS/RF, X-FAB Group. 6. Dr. Masoud Kahrizi, Scientist, Principal - RF/Wireless Mobile Platform, Broadcom.
	Berkeley Design Automation, Inc.	Paul Estrada, Chief Operating Officer, Berkeley Design Automation, Inc. Panelist. Bio: Prior to BDA, Estrada spent nearly 6 years at Cadence Design Systems where he was general manager for Encounter Test, corporate vice president of strategy, and launched the Virtuoso custom design platform, Encounter digital design platform, and Incisive functional verification platform. In 1996, he co-founded 0-In Design Automation and helped pioneer assertion-based verification as their VP verification engineering. From 1992-1996 Estrada was responsible for synthesis marketing at Synopsys during that business’ explosive growth period. He also has experience in the semiconductor, wireless communication, and industrial automation industries. Estrada holds engineering degrees with top honors from Stanford University and the University of Illinois. He also holds three patents.
	UCLA	Dr. Sudhakar Pamarti, Assistant Professor of Electrical Engineering, University of California, Los Angeles. Panelist. Bio: Dr. Sudhakar Pamarti is an assistant professor of electrical engineering at the University of California, Los Angeles, where he teaches and conducts research in the fields of mixed-signal circuit design and signal processing. He received the Bachelor of Technology degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur in 1995, and the M.S. and the Ph.D. degrees in electrical engineering from the University of California, San Diego in 1999 and 2003, respectively. Prior to joining UCLA, he has worked at Rambus Inc. (‘03-`05) and Hughes Software Systems (‘95-`97) developing high speed I/O circuits and embedded software and firmware for a wireless-in-local-loop communication system respectively. Dr. Pamarti has, in the past, served on the editorial board of the IEEE Transactions on Circuits and Systems II and is a recipient of the NSF CAREER award.
	Broadcom Corporation	Dr. Masoud Kahrizi, Scientist, Principal - RF/Wireless, Broadcom Corporation. Panelist. Bio: Dr Masoud Kahrizi is a Principal Scientist at Broadcom Corporation and is responsible for RF system integration in the next generation system on chip radio for cellular communications. Dr. Kahrizi graduated from Syracuse University, Syracuse, NY, in 1992 with a Ph. D. in Electrical Engineering. He joined the Department of Electrical Engineering, Tarbiat Modares University (TMU) , Tehran. During 1997-99, he was the technical manager at Telecommunication Research Center (ITRC), Tehran, where he developed an RF section for the Base Station of GSM wireless systems. In April 1999, he left TMU as associate professor and joined the University of Waterloo in Canada where he developed and implemented an innovative approach for filter diagnosis and computer tuning of RF & Microwave filters in collaboration with Ericsson Canada Inc. Since 2000, Dr. Kahrizi has worked as a senior system architect in RFIC and systems design on multi-standard transceiver for GSM, WCDMA and WLAN. From 2005 to 2009, Dr. Kahrizi worked as a senior principal engineer to develop integrated multi-standard radio for 2.5 and 3G at Skyworks solutions inc., Irvine, CA. Dr. Kahrizi is a senior member of IEEE and has more than 18 years of experience in RF/Microwave and Wireless Communication and has authored or co-authored more than 20 technical papers, patents and conference presentations in the areas of wireless communication, RF, and microwave design. Since 2007, Dr Kahrizi has been acted as Vice-Chairman of Orange County IEEE EDS/MTT Joint Chapter where has provided or organized technical session in the area of his expertise.
	X-FAB Group	Mr. Olaf Zinke, Product Line Manager AMS/RF, X-FAB Group. Panelist. Bio: As Product Line Manager, Olaf Zinke is responsible for the Analog/Mixed-signal and RF product line. Prior to joining X-FAB he worked for Cadence Design Systems as Senior Product Marketing Manager responsible for Analog/Mixed-signal simulation technologies, in particular the Virtuoso AMS Designer Product. Earlier, Olaf worked as a Corporate Application Engineer specializing on AMS behavioral modeling languages at Cadence and Analogy, and prior to this as an IC Design Engineer in the field of Electronic Control Units for Automotive Applications at Continental Teves. Olaf has 20 years of experience in the design, application and marketing of Semiconductor and Electronic Design Automation products. He holds a Master of Science degree in Theory of Electrical Engineering from the Technical University of Ilmenau, Germany.
	Cypress Semiconductor	Dr. Babak Taheri, Vice President, Technical Staff, in charge of IP and new product development, Cypress Semiconductor. Panelist. Bio: Babak Taheri is vice president of worldwide corporate IP at Cypress Semiconductor Corp. whose team headed up development of Cypress’s multitouch technology, now in volume production. Prior to his current role, Taheri was responsible for corporate product development, where he served as director of design, establishing more than ten design centers of excellence worldwide. Prior to re-joining Cypress, Dr. Taheri was vice president of engineering at InvenSense Inc., a fabless MEMS semiconductor company focusing on high-volume product delivery to consumer markets. Dr. Taheri has more than 25 years of semiconductor industry experience that includes founding Integrated Biosensing Technologies, a biomedical corporation. He also has held key positions at Intel, SRI International, Redwood Microsystems, and Apple. Dr. Taheri holds a doctorate degree in electrical engineering & Neurosciences from the University of California at Davis, and more than 20 U.S. patents.
	Lunch	Lunch
		Panel: “Emerging Technologies, Trends, and Possibilities in Designing Multicore SoC Platforms. "
	Panel Savant Company Inc. Bluespec, Inc. Real Intent Target Compiler Technologies EDA360 Cadence Design Systems Zocalo Tech, Inc. UCR	Moderator: Farhad Mafie, Savant Company Inc., President & CEO. SoC Conference Chairman & Developer. Panelists: 1. George Harper, VP Marketing, Bluespec, Inc. 2. Dr. Pranav Ashar, Real Intent CTO, Real Intent. 3. Steve Cox, VP Business Development, Target Compiler Technologies. 4. Steve Leibson, EDA360 Evangelist. Cadence Design Systems. 5. Howard Martin, President of Zocalo Tech, Inc. 6. Dr. Philip Brisk, Assistant Professor, Department of Computer Science and Engineering Bourns College of Engineering University of California, Riverside.
	Panelist Bluespec, Inc.	George Harper, VP Marketing, Bluespec, Inc. Panelist Bio: Mr. Harper has more than 25 years of marketing and engineering experience from the semiconductor, communications, and storage industries. He has overall responsibility for Bluespec's product planning and marketing initiatives. Previously, Mr. Harper was director of marketing at Trebia Networks, where he managed the product planning and marketing initiatives for a storage network processor family. Prior to that, he held senior marketing positions at Conexant Systems (formerly Maker Communications) and Shiva Corporation, and engineering positions at LSI Logic, in both California and Massachusetts, specifically in the areas of chip design and microprocessor sales. Harper has a B.S. and an M.S. in electrical engineering from Stanford University and an M.B.A. from Harvard University.
	Panelist Real Intent	Dr. Pranav Ashar, CTO, Real Intent. Panelist Bio: Dr. Pranav Ashar, Real Intent CTO, brings two decades of EDA expertise to Real Intent. Pranav received his M.S. and Ph.D. in EECS with emphasis on EDA from the University of California, Berkeley in 1989 and 1991, respectively. He then joined NEC Labs in Princeton, NJ where he developed a number of EDA technologies that have influenced the industry. One of his important accomplishments there was in raising the prominence of formal methods in VLSI design through the creation of a very successful Verification Department and the development and widespread deployment in EDA tools of practical methods for formal verification. Through his leadership, the department also parlayed its formal methods expertise into practical methods for formal analysis in software engineering that have been deployed in the field. Pranav also created a successful department at NEC Labs for the application of automata and machine learning methods in the management of large-scale distributed systems. Pranav previously served as CTO at Real Intent from 2004 through 2006. In the interim, he served as CTO at a mobile-phone security company called NetFortis that he co-founded for which he developed low-energy high-performance algorithms for malware detection, and Chief Scientist at a simulation acceleration company called Liga Systems that was based on technology developed by him at NEC Labs for custom-VLIW based parallel simulation that was recently able to demonstrate a reduction in simulation time from 21 days to about 1 day on a 25 Million gate design. Pranav has authored about 70 publications in refereed conferences and journals with approximately 800 citations, and co-authored a book titled "Sequential Logic Synthesis". He has 35 patents granted and pending, many of which have been licensed or part of business enablement. Pranav has been on committees of ICCD, ICCAD and IWLS. He was ICCD Program Chair in 2004 and 2005, and ICCD General Chair in 2006. Pranav is an adjunct faculty in the CSEE department at Columbia University where he has taught graduate and undergraduate courses on VLSI design automation, VLSI Verification, and VLSI design. Pranav has also taught a graduate course on Switching Theory in the EE department at Princeton University.
	Panelist Target Compiler Technologies	Steve Cox & Gert Goossens, Target Compiler Technologies - Leuven, Belgium and Boulder, CO USA. Panelist Bio: Steve Cox joined Target Compiler Technologies in 2006 and leads Target’s North American activities. Steve has a long history of innovation in the design and verification of processors and SoCs, including work at companies such as Accelchip, Apple, Ball Aerospace, Cadence, Cisco, Conexant, Intel, Motorola/Freescale, Nortel, and Solbourne Computer. Steve holds patents in the area of transaction-based verification of SoCs and is an alumnus of the University of Colorado. Steve currently resides in Boulder.
	Panelist Zocalo Tech, Inc.	Howard L. Martin, Founder and President of Zocalo Tech, Inc. Panelist. Bio: Over 30 years of experience in EDA sales and management specializing in early stage startups. He was one of the first salesmen when EDA emerged as a distinct market working for Daisy Systems. In the early nineties immediately after the merger of ECAD and SDA to form Cadence and subsequent acquisition of Gateway, he was responsible for the sales and support for the Western US. He was a founder and President of SpeedGate, Inc. acquired by Mentor Graphics in 2001. He is presently a founder and President of Zocalo Tech, Inc. Martin has a BS in Aeronautical Engineering and MS in Physics.
	Panelist EDA360 Cadence Design Systems	Steve Leibson, EDA360 Evangelist. Cadence Design Systems. Panelist Bio: Steve Leibson literally wrote the books on IP-based SOC design — “Designing SOCs with Configured Cores,” published in 2006 and “Engineering the Complex SOC,” co-authored with Dr. Chris Rowen and published in 2004. Steve has been evangelizing IP-centric SOC design since 2001 through articles, White Papers, books and book chapters, Webinars, videos, invited keynote presentations, conference presentations, and in-booth trade show presentations around the world. He is now the EDA360 Evangelist and Marketing Director at Cadence Design Systems, a leading EDA vendor specializing in system and chip-level design tools, design IP and IP design platforms, and verification IP. Prior to joining Tensilica as Technology Evangelist, he was VP of Content for Reed-Elsevier/Microdesign Resources, managed and ran the Microprocessor Forum, and he has served as editor in chief of the Microprocessor Report newsletter, EDN Magazine, and Embedded Developer’s journal where he set publication vision and mission and managed editorial and production teams of experienced journalists and writer/engineers. He has many years of experience in persuasively communicating with the electronic design community across a broad range of topics and has made a particular study of reaching the extremely elusive design community for the purpose of lead generation through diverse channels including the Internet, blogs, social media, and online video.
	Panelist UCR	Dr. Philip Brisk, Assistant Professor, Department of Computer Science and Engineering Bourns College of Engineering University of California, Riverside. Panelist Bio: Philip Brisk received his B.S., M.S., and Ph.D. degrees, all in Computer Science, from UCLA in 2002, 2003, and 2006 respectively. From 2006-2009, he was a postdoctoral scholar in the Processor Architecture Laboratory at the Ecole Polytechnique Federale de Lausanne (EPFL) in Switzerland. Since 2009, he has been an Assistant Professor in the Department of Computer Science and Engineering at the University of California, Riverside. Dr. Brisk's research interests include embedded processor architecture and customization, FPGAs and reconfigurable computing, compilers, VLSI-CAD, computer arithmetic, and emerging microfluidic technologies. He has received best paper awards at CASES 2007 and FPL 2009, and has been nominated for best paper awards at DAC 2007 and HiPEAC 2010. He is a member of the ACM and IEEE.
	Xilinx Keynote	Dr. Ivo Bolsens, Senior Vice President and Chief Technology Officer, Xilinx Inc. Keynote Bio: Ivo Bolsens is senior vice president and chief technology officer (CTO), with responsibility for advanced technology development, Xilinx research laboratories (XRL) and Xilinx university program (XUP). Bolsens came to Xilinx in June 2001 from the Belgium-based research center IMEC, where he was vice president of information and communication systems. His research included the development of knowledge-based verification for VLSI circuits, design of digital signal processing applications, and wireless communication terminals. He also headed the research on design technology for high-level synthesis of DSP hardware, HW/SW co-design and system-on-chip design. Bolsens holds a PhD in applied science and an MSEE from the Catholic University of Leuven in Belgium.
	Intel	Durgesh Srivastava, Principal Engineer in the Embedded and Communications Group. Intel’s ATOM™ based SoC – Tunnel Creek. Abstract: Tunnel Creek is Intel’s next generation ATOM™ based SoC. In this talk Durgesh will talk about the 3 cornerstones of innovation namely platform flexibility, reduced bill of materials and performance density and will showcase application case studies with examples on In-Vehicle Infotainment, IP Media Phone, Programmable Logic Controller and Electronic Cash Register. Bio: Durgesh Srivastava is Principal Engineer in the Embedded and Communications Group at Intel. He is driving the silicon and system architecture for Atom based System on a Chip (SOC) for Embedded group. He has been at Intel for almost fourteen years. He holds Masters degree from Hong Kong University of Science and Technology, Hong Kong and Bachelors from Indian Institute of Technology, Kanpur, India, in Electrical Engineering.
	University of Southern California	Dr. Mel Breuer, of Electrical Engineering-Systems Department of Electrical Engineering-Systems University of Southern California. Novel ways to use future SoC technologies. Abstract: Technological achievements have made it possible to: fabricate CMOS circuits with over a billion transistors; implement Boolean operations using quantum devices and/or the spin of an electron; implement transformations using bio and molecular based cells. Problems with many of these technologies are due to such factors as process variations, defects and impurities in materials and solutions, and noise. Consequently, many systems built from these technologies operate imperfectly. Luckily there are many complex and large-market systems (applications) that tolerate acceptable though not always correct results. In addition, there is emerging a body of mathematical analysis related to imperfect computation. In this presentation we first introduce the concepts of acceptable error-tolerance and acceptable performance degradation, and demonstrate how important attributes of these concepts can be quantified. We interlace this discussion with several examples of systems that can effective employ these two concepts. Next we mention several emerging technologies that motivate the need to study these concepts as well as related mathematical paradigms. Bio: Melvin A. Breuer received his Ph.D. in electrical engineering from the University of California, Berkeley, and is the Charles Lee Powell Professor of Electrical Engineering and Computer Science at the University of Southern California. He was Chairman of the Department of Electrical Engineering-Systems from 1991-1994, and again from 2000-2003. He was Chair of the Faculty of the School of Engineering, USC, for the 1997-98 academic year. His main interests are in the area of computer-aided design of digital systems, design-for-test and built-in self-test, and VLSI circuits. Dr. Breuer is the editor and co-author of Design Automation of Digital Systems: Theory and Techniques, Prentice-Hall; editor of Digital Systems Design Automation: Languages, Simulation and Data Base, Computer Science Press; co-author of Diagnosis and Reliable Design of Digital Systems, Computer Science Press; co-editor of Computer Hardware Description Languages and their Applications, North-Holland; co-editor and contributor to Knowledge Based Systems for Test and Diagnosis, North-Holland; and co-author of Digital System Testing and Testable Design, Computer Science Press 1990 and reprinted in 1995 by the IEEE Press. He has published over 230 technical papers and was formerly the editor-in-chief of the Journal of Design Automation and Fault Tolerant Computing, on the editorial board of the Journal of Electronic Testing, the co-editor of the Journal of Digital Systems, and the Program Chairman of the Fifth International IFIP Conference on Computer Hardware Description Languages and Their Applications. He is a co-author of a paper that received an honorable mention award at the 1997 International Test Conference, a co-author of a paper nominated for the best paper award at the 1998 Design Automation and Test in Europe Conf., a co-author of a paper published in the 1998 International Test Conference that was selected to be in a compendium of significant papers over the last 35 years, and a co-author of the best paper at the 2000 Asian Test Symposium. He is a Life Fellow of the IEEE; was a Fulbright-Hays scholar (1972); received the 1991 Associates Award for Creativity in Research and Scholarship from the University of Southern California, the 1991 USC School of Engineering Award for Exceptional Service, the IEEE Computer Society’s 1993 Taylor L. Booth Education Award, an Okawa Foundation Research Grant in support of research to “Increase the effective yield of VLSI chips via design and test” (2003), and the first (2000) Engineering Faculty Council Award for Outstanding Meritorious Service to the USC School of Engineering. He was the keynote speaker at the Fourth Multimedia Technology and Applications Symposium, 1999; the Ninth Asian Test Symposium, 2000; the International Conference on Computer Design (ICCD), 2004; the Annual Symposium on VLSI (ISVLSI), 2005; the IEEE VLSI Test Symp., 2008, and an invited speaker at the Thirteenth Asian Test Symposium, 2004. The Test Technology Technical Council of the IEEE Computer Society hosted a forum on October 26, 2006 at the Hyatt Regency Hotel, Santa Clara, California to “celebrate Professor Melvin A. Breuer’s illustrious career and recognize his contributions to VLSI areas of design automation, design for testability, fault tolerance and test; and the influence he had on the industry and academia as an educator and a mentor.”
	MoSys, Inc.	Mark Baumann, Director, Product Definition and Applications. MoSys, Inc. Breaking Bandwidth Density Barriers With GigaChiptm Serial Interface and the Bandwidth Enginetm. Abstract: As Network equipment manufacturers design equipment for 100G and beyond the density of bandwidth not only increases at the edges of the cards but also at the edges of the silicon devices. NPUs, ASICs, and FPGAs are running out of pins to meet the bandwidth demands with today’s memory. Virtually all ASIC, FPGA and NPU use the DDR style interface to communicate with all types of high speed memory and coprocessors from DDR3, QDR, RLDRAM to Knowledge Based Processors. Because clock rates on the DDR interface have not kept up with the growth in serial communication rates, designers are approaching an impasse. In order to put memory bandwidth on an equal footing with line rates, memories and coprocessors must adopt SerDes based I/O. To meet the widening gap new memory and ALU called Bandwidth Engine was announced along with an new serial interface called GigaChip™ Interface was announced to address the challenges of increased bandwidth density and the increased demand in random memory access rates. The GigaChip Interface is CE-11 compatible, short-reach, low-power serial interface which enables highly efficient, high-bandwidth, low-latency performance chip to chip communication at the board level. Similar to the fundamental performance breakthrough achieved by the move to double data rate (DDR) style interfaces in the late 90’s, the GigaChip Interface will provide the next breakthrough in chip-to-chip communications using differential SerDes technology. A 16-lane GigaChip Interface can replace up to four separate 78-pin DDR parallel interface busses to memory, which represents a memory performance increase of 4 times, while reducing system power and interface costs by 2 to 3 times. Such bandwidth density increases will be required to realize line cards with aggregate through put beyond 100G in future networking systems. The Gigabit Interface has adopted the open CEI-11 electrical transport standard making use of existing electrical ecosystem in order to shorten time to market for introduction of system designs. This presentation will describe the GigaChip serial interface and the show how an increase in 3 to 4 bandwidth density vs silicon area over today’s DDR style interface can be achieved. Bio: Mr. Baumann brings more than 10 years of engineering management experience in silicon design, printed circuit board design and product definition to MoSys. Prior to joining MoSys, he served as the Cisco Account Manager for NetLogic Microsystems, overseeing the technical support and sales teams servicing Cisco Systems. Previous to NetLogic, Mr. Baumann served as the Director of Engineering for Integrated Device Technology where he built the design team and managed development of IP co-processor products. During his tenure at IDT, he also held the positions of Memory Products Manager for the Systems Technology Group, Member of the Technical Staff, and Field Applications Engineer. Prior to IDT, Mr. Baumann held design engineering and design management roles for Raytheon. Mr. Baumann holds a Bachelor of Science in Electrical Engineering from Manhattan College in New York, New York and has been awarded more than ten patents to date.
	Cadence Design Systems	Thomas L. Anderson, Product Management Group Director, Cadence Design Systems. UVM: Essential Methodology Standardization for Multi-Core SoCs. Abstract: Standardization of design and verification languages has been an accepted part of the electronics industry for nearly 25 years. Design and verification engineers take it for granted that Accellera and IEEE will define new language standards and evolve existing ones. Until very recently, verification methodologies and supporting libraries have fallen outside of standardization activities. At the same time, the ever-increasing complexity of today’s SoCs, especially those with multiple cores, has put tremendous pressure on the verification process. The industry has been demanding a methodology standard. This talk describes the new Universal Verification Methodology (UVM) standard from Accellera, released in May 2010. The talk discusses the impact that the UVM has made on the development of SoCs and provides a brief history of its development, including the relationship to the Open Verification Methodology (OVM), which was introduced at the SoC Conference in 2008. Particular focus is given to the value that the UVM and its vendor/partner ecosystem bring to the developmers of multi-core SoCs. This talk is essential for SoC verification engineers, designers tasked with verification responsibilities, and SoC project managers. Bio: Thomas L. Anderson is a Product Management Group Director at Cadence, where his responsibilities include all verification software products. His previous positions include Director of Technical Marketing at Synopsys, Vice President of Applications Engineering at 0-In Design Automation, and Vice President of Engineering at Virtual Chips. Mr. Anderson has presented more than 100 conference talks and published more than 150 papers and technical articles. He holds an MS in Electrical Engineering and Computer Science from MIT and a BS in Computer Systems Engineering from the University of Massachusetts at Amherst.
	Seagate	Patrick Ryan, Vice President – Research and Development, Memory Products Group – Alternative Technology Group, Bloomington, Minnesota, Seagate. The Implication of Emerging Memory on System-on-Chip Design. Abstract: As device dimensions shrink into the nanometer regime, most of the current dominant memory technologies, e.g., SRAM, DRAM and Flash, are facing severe scalability challenges. Many alternative technologies have emerged, including Phase Change Memory, Resistive Memory and Magnetic Memory to meet these challenges. These emerging memory technologies promise many attractive characteristics, such as high-density, high-speed access, zero standby power, non-volatility, virtually unlimited endurance and CMOS process compatibility, etc. These unique properties provide many promising opportunities for the future System-on-Chip (SoC) designs. As the next-generation of magnetic memory technology, Spin-Transfer Torque Random Access Memory (STT-RAM) has recently attracted increasing attention from the solid state circuit community. This talk will first outline the fundamentals of STT-RAM technology and include the efforts in research and development of new materials, devices, and circuit architectures ongoing in the industry. The implication of the advances in STT-RAM technology on SoC and other applications will be also be discussed. A perspective on future research necessary for continued STT-RAM advancement, essential in meeting the progression of Moore’s law, will be given. Bio: Patrick Ryan, Vice President – Research and Development, Memory Products Group – Alternative Technology Group, Bloomington, Minnesota. Pat Ryan has worked in the HDD industry for over 20 years, joining Control Data Corporation(Magnetic Peripherals) as a design engineer in 1984 and then joining Seagate in 1989.(when Seagate purchased, Magnetic Peripherals) He has worked on Thin-Film Head Technology for much of his career holding engineering and management positions in both development and manufacturing. He is currently Vice President for Alternative Technology Development where he manages a team responsible for advanced Solid State Drive (SSD) development. Prior to this he held the post of Chief Technologist for Head Technology in the Recording Heads - Advanced Transducer Development. Past work responsibilities have included technical management of International R+D team (US + Ireland) in the development and integration of world class transducer devices for the disk drive market. He has a strong background in recording, magnetics and micro-magnetics, with emphasis on advanced devices and materials. Over the course of his career he has been a key contributor to delivery of new capital investments in Minnesota that have helped expand Seagate’s presence here. Currently, Pat serves on the Board of MN Nano, private sector advocacy organization promoting nanotechnology in Minnesota, where he has been Chair for the past 3 years. He has also served on the Technology Advisory boards for Veeco Instruments, and Imago Instruments (Startup - Atom Probe) He has been on the Industrial Advisory Board for U of Minnesota Electrical and Computer Engineering department for the past 4 years. Pat holds a degree in Electrical Engineering (1983), from the University of Minnesota. Currently, he also holds more than 25 patents in nanotechnology including magnetic devices, MEMs, and thin-film technology.
		Day TWO Nov. 4, 2010 SoC Conference Program Agenda*
		Software Strategies, Planning, and Solutions, for Embedded Multicore SoC Platform Development. Track Chairman: Farhad Mafie, SoC Conference Chairman, Savant Company Inc., President & CEO.
	Savant Company Inc.	Farhad Mafie, SoC Conference Chairman, President and CEO of Savant Company Inc. Farhad Mafie is President and CEO of Savant Company Inc., a technology marketing company in Irvine, CA. Savant specializes in marketing and sales of semiconductor IC/IP products, SoC/ASIC services and solutions, as well as providing targeted technical- and business-related training seminars and conferences globally. He has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. He is the former Vice President of Marketing and Engineering at Toshiba Semiconductor. He has also worked in strategic marketing, project and design engineering at Lucent Technologies, Unisys, and MSI Data. Farhad has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. He is an author and a translator, and his articles have been published in a variety of journals and Web-based magazines on technology and political affairs. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units. Farhad is an active member of IEEE, and he is the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN). He is also a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs.
	Southern California Edison	Mike Sanders, PMP, Project Manager. Advanced Multitasking - Do More, Work Less, Be Happy. Abstract: Multitasking seems to be one of required skill sets in today’s highly-tasked workforce. As a matter of fact, it seems that if you’re not multitasking, there must be something wrong with you - you’re not perceived as a high achiever. In his presentation, Mike discusses multitasking as you have never heard it before; how it really works, what it can do “for” you, what it can do “to” you, research about it, proven methods and tools to improve task performance, and measurements for “advanced” multitasking in today’s complex workforce. He will show you how multitasking can be leveraged by your three brains (yes, three) to maximize your output while working fewer hours, with less anxiety, and having more fun. This is powerful material, so get ready to explode onto your work scene – the next day! Can you handle even more success? Bio: Mike Sanders is a Project Manager at Southern California Edison and PMP. He is Past President of the local Project Management Institute (PMICIE) and President of the Society for Technical Communication (IESTC). Mike has over 15 years experience in project management and over 10 years in the field of technical writing. He has taught and trained at the university, college, and industry levels and is a regular public speaker. Mike has presented Advanced Multitasking concepts at PMI's Inland Empire, Los Angeles, Orange County, San Diego, and Los Padres Chapters, at the IIBA Orange County Chapter, at San Diego's Naval Weapons Center, at the SQCAA Orange County and Inland Empire Chapters, at the Southern Technology Conference (SoTeC), at PMI San Diego’s Annual Conference, regularly through the University of California Irvine's Project Management Certification Program, and at numerous companies throughout Southern California.
	Symbian Foundation Limited	Oliver Gunasekara, Head of North America Global Alliances, Symbian Foundation. Symbian Smartphone Operating System Past, Present & Future. Abstract: This presentation explores the driving requirements for embedded multicore SoC platforms in smart mobile devices. The speaker will compare and distinguish between a Smartphone from 2000 (ARM7), 2010 model (ARM Cortex-A8) and 2015 (ARM 'Eagle' & 'Kingfisher'). He will discuss the demands and challenges being introduced by future use cases, which demand increased performance, increased power efficiency and embedded security. The speaker will compare Symbian OS with various Smartphones’ operating systems and discusses the OS porting challenges, performance issues, power consumption, and other considerations for selecting an Operating System for these new complex devices/applications. The presentation will also break-down the reasoning behind the industry’s need for more software standards around SoC interfaces, avoiding the duplicated and undifferentiated work by different semiconductor vendors. Bio: Oliver is part of the management team responsible for encouraging adoption and contribution of the Symbian Platform across strategic manufacturers, semiconductors and operators. He is based in Silicon Valley. Oliver joined ARM Ltd in 1995. The UK’s most successful technology start-ups which had an IPO in 1998. He was tasked with getting ARM technology into mobile handsets. Initially working in Europe, he latter relocated to Japan in 2008. In 2002 he became the Global Director of Mobile Solutions delivering an almost 100% market share today. In 2005 he became the Vice President corporate business development and M&A relocated to the SF bay area. In 2007 he joined a video fabless start-up called W&W Communications as Vice President of Mobile business which was acquired in 2008 by Cavium Networks. In May 2009 he joined the non-profit open source Symbian Foundation. Oliver holds a Bachelor's degree with honours in Electrical and Electronic Engineering from the University of Greenwich London, UK.
	Intel	David Stewart, Manager of the Embedded Linux Engineering team. Creating Coherence in SoC Linux. Abstracts: TBA. Bio: David Stewart is the manager of the Embedded Linux Engineering team within the Open Source Technology Center (OTC), part of the System Software Division of the Software and Services Group (SSG) of Intel Corporation. Before the formation of this team, David held a variety of software development management positions in SSG and in Intel’s Desktop Boards and Systems division and Server Products group. Prior to joining Intel in 1997, David held management and engineering positions in consumer software products and operating system development, including Sequent, Tektronix. David holds a BS and MS in Computer Science from Colorado State University in Fort Collins, which he received in 1983. David has given keynotes and presentations in over 40 technical conferences, and a series of popular technical videos on YouTube.
	MontaVista	James Ready, CTO. Beyond Virtualization: A Novel Software Architecture for Multi-Core SOCs. Abstract: TBA. Bio: James Ready is the founder of MontaVista software and a recognized authority in the embedded real-time software industry. He developed the first commercially viable, real-time operating system: VRTX kernel. He founded Ready Systems in 1980, which merged with Microtec Research, went public in 1994, and was acquired by Mentor Graphics in 1995. During this period, Mr. Ready served as president of Ready Systems and as CTO of Microtec and Mentor. In 1999, Mr. Ready founded MontaVista Software to bring the Linux operating system to the embedded systems market. He earned a BA from the University of Illinois and an MA from the University of California, Berkeley.
	Morning Break	Morning Break
	Mindspeed Technologies, Inc. Keynote	Raouf Y. Halim, Chief Executive Officer. Mindspeed Technologies, Inc. Keynote Bio: Mr. Halim has been a director since January 2002 and our chief executive officer since June 2003. He was the senior vice president and chief executive officer of the internet infrastructure business of Conexant from February 2002 to June 2003 and the senior vice president and general manager, network access division, of Conexant from January 1999 to February 2002.
		Panel: “Software Strategies, Planning, and Solutions, for Embedded Multicore SoC Platform Development.”
	Panel Embedded Insights Inc Microsoft MontaVista ARM Intel Conexant Carbon Design Systems Signum Systems Corp.	Robert Cravotta is the principal analyst at Embedded Insights Inc, and Contributing Editor at EDN Magazine. Moderator Bio: Robert Cravotta is the principal analyst at Embedded Insights Inc. As a former Technical Editor covering Embedded Processing at EDN, Robert has been following and commenting on the embedded processing space since 2001. His expertise includes software development and system design using microprocessors, microcontrollers, digital signal processors (DSPs), multiprocessor architectures, processor fabrics, coprocessors, and accelerators, plus embedded cores in FPGAs, SOCs, and ASICs. Robert's embedded engineering background includes 16 years as a Member of the Technical Staff at Boeing and Rockwell International working on path-finding avionics, power and laser control systems, autonomous vehicles, and vision sensing systems. Panelists: 1. Toby McAuliffe, Lead Account Manager for Windows Embedded US, Microsoft. 2. James Ready, CTO, MontaVista. 3. Ketan Paranjape, Software Program Manager, ATOM and SoC Development, Intel. 4. Dr. Shireesh Verma, Imaging and PC Media Group, Conexant Systems, Inc. 5. Bill Neifert is the CTO and founder of Carbon Design Systems. 6. Robert Chyla, VP of Research and Development, Signum Systems Corp.
	Panelist Microsoft	Toby McAuliffe, Lead Account Manager for Windows Embedded US, Microsoft. Panelist Bio: Toby McAuliffe is an 11 year veteran of Microsoft, spending time in multiple organizations during his career. Starting as an Account Executive in the late 90’s, Toby has held various roles mostly focused in Partner Management and Business Development. After moving to the OEM Embedded Division in 2007, Toby started in the group managing Microsoft’s partnership with one of North America’s largest Distributors of Windows Embedded Licensing, and is now responsible for managing the entire North American Indirect Sales team. Toby graduated from North Carolina Wesleyan College, earning a BS degree double majoring in Mathematics and Computer Science.
	Panelist MontaVista	James Ready, CTO, MontaVista. Panelist Bio: James Ready is the founder of MontaVista software and a recognized authority in the embedded real-time software industry. He developed the first commercially viable, real-time operating system: VRTX kernel. He founded Ready Systems in 1980, which merged with Microtec Research, went public in 1994, and was acquired by Mentor Graphics in 1995. During this period, Mr. Ready served as president of Ready Systems and as CTO of Microtec and Mentor. In 1999, Mr. Ready founded MontaVista Software to bring the Linux operating system to the embedded systems market. He earned a BA from the University of Illinois and an MA from the University of California, Berkeley.
	Intel	David Stewart, Manager of the Embedded Linux Engineering team. Panelist Bio: David Stewart is the manager of the Embedded Linux Engineering team within the Open Source Technology Center (OTC), part of the System Software Division of the Software and Services Group (SSG) of Intel Corporation. Before the formation of this team, David held a variety of software development management positions in SSG and in Intel’s Desktop Boards and Systems division and Server Products group. Prior to joining Intel in 1997, David held management and engineering positions in consumer software products and operating system development, including Sequent, Tektronix. David holds a BS and MS in Computer Science from Colorado State University in Fort Collins, which he received in 1983. David has given keynotes and presentations in over 40 technical conferences, and a series of popular technical videos on YouTube.
	Panelist Conexant Systems, Inc.	Dr. Shireesh Verma, Imaging and PC Media Group, Conexant Systems, Inc. Panelist Bio: Shireesh Verma is currently with Conexant Systems Inc. Prior to that he has held research and development positions at Qualcomm Inc. and Marvell Semiconductor Inc. He has been involved in extensive research on various aspects of verification like, automatic generation and evaluation of functional and syntactic coverage models, coverage feedback driven test generation, behavioral error models, low power verification techniques, etc for the past 9 years. He obtained his PhD degree in Information and Computer Science from the University of California Irvine. He has led several in-house Design and Verification tool development efforts during his industrial stints. He has published numerous conference papers, journal and magazine articles and a book chapter. He has also delivered numerous invited tutorials and has been invited at several panels in these areas. He serves on the editorial board of Journal of Low Power Electronics (JOLPE). He is also a member of the Accellera P1801 Low Power Working Group and the IEEE Design Automation Standards Committee. He is a member of the Technical Program Committees of "ACM/IEEE Design Automation and Test in Europe (DATE) Conference", "IEEE International High Level design Validation and Test (HLDVT) Workshop", and "International Symposium on Quality Electronic Design (ISQED)". He is also a member of the organizing committee (Publicity chair) of the HLDVT 2009.
	Panelist Carbon Design Systems	Bill Neifert is the CTO and founder of Carbon Design Systems. Panelist Bio: Bill Neifert is the CTO and founder of Carbon Design Systems. Bill has 18 years of electronics engineering experience with more than 15 years in EDA including C-Level Design and Quickturn Systems where he managed technical resources and sales engagements for the eastern half of the United States. Bill started his career as an ASIC design and verification engineer at Bull. Bill has a BS and MS in Computer Engineering from Boston University.
	Panelist Signum Systems Corp.	Robert Chyla, VP of Research and Development, Signum Systems Corp. Panelist Bio: Robert Chyla joined the Signum Systems Inc. in USA in 1996. The company founded in 1980 is a US-based maker of high-end JTAG and trace emulation and debug tools. As VP of R&D Robert is responsible for SW architecture and SW/HW interfacing of JTAG debugging and trace tools. He is trying to advocate usage of high-end debug tools during development of modern ARM-based embedded systems. Recently he is focusing on JTAG and trace solutions for multi-core and embedded Linux systems. Before joining Signum he was working as an assistant professor for few years and engaged into high-end 3D graphics rendering software development with Japanese company Integra Inc. He earned masters in Computer Science from Wroclaw Technical University, Poland.
	Lunch	Lunch
		Green Chips: Technologies, Tools, and Methodologies in Designing Ultra Low-Power Multicore SoCs. Track Chairman: Dr. Nader Bagherzadeh, Professor, Electrical Engineering and Computer Science, UC Irvine.
	University of California, Irvine	Dr. Nader Bagherzadeh, University of California, Irvine. General Purpose Processors (GP) vs. Application Specific Processors (ASP), what is the future for multicore designs with 1000's of IPs? Abstract: In this talk first a brief overview of multicore architectures is discussed. Next, the critical issue of homogeneous versus heterogeneous processing nodes for the future multicore architectures is analyzed, and areas that require further research and development are identified. Finally. concluding remarks are made regarding future designs. Bio: Dr. Nader Bagherzadeh has been involved in research and development in the areas of computer architecture, reconfigurable computing, VLSI chip design, and computer graphics. For almost ten years ago, he was the first researcher working on the VLSI design of a Very Long Instruction Word (VLIW) processor. Since then, he has been working on multithreaded superscalars and their application to signal processing and general purpose computing. His current project at UC, Irvine is concerned with the design of coarse grain reconfigurable pixel processors for video applications. The proposed architecture, called MorphoSys, is versatile enough to be used for digital signal processing tasks such as the ones encountered in wireless communications and sonar processing. DARPA and NSF fund the MorphoSys project (total support $1.5 million). Dr. Bagherzadeh was the Chair of Department of Electrical and Computer Engineering in the Henry Samueli School of Engineering at University of California, Irvine. Before joining UC, Irvine, from 1979 to 1984, he was a member of the technical staff (MTS) at AT&T Bell Laboratories, developing the hardware and software components of the next-generation digital switching systems (#5 ESS). Dr. Bagherzadeh holds a Ph.D. in computer engineering from The University of Texas at Austin. As a Professor, he has published more than a hundred articles in peer-reviewed journals and conference papers in areas such as advanced computer architecture, system software techniques, and high performance algorithms. He has trained hundreds of students who have assumed key positions in software and computer systems design companies in the past twelve years. He has been a Principal Investigator (PI) or Co-PI on more than $2.5 million worth of research grants for developing next-generation computer systems for solving computationally intensive applications related to signal and image processing.
	ARM	Dr. David Flynn, a Fellow in R&D at ARM Ltd. Practical state retention and power gating applied to SoC Subsystems. Abstract: Power Gating is now a well understood technique for reducing static leakage power when circuits are idle. State Retention enhancements in hardware can address fast wake-up latency and transparency to system software but have area, performance and robustness/reliability impacts. This paper addresses practical application of State Retention Power Gating, SRPG, applied to a cached CPU subsystem – ARM1176JZFS case study. Multi-Voltage support in EDA design flows now offered by power intent formats, UPF and CPF, address the low level implementation challenges; the tutorial covers what matters from the system and RTL designer perspective, and provides an in-depth view of the realizable power savings - and verification implications. Real world issues such as testability and retention state integrity are covered. The case study covers silicon implementation and detailed evaluation at 65nm. Conclusions are then drawn as to which techniques show the best promise for minimal area/performance impact with maximal leakage power savings. Table of Contents of the presentation: 65nm – performance/power trade-offs, Low-power approaches – CPU and SOC, Low-power building blocks – physical IP, CPU (ARM1176JZFSTM) power management, SoC low power diagnostics, Analysis (Typical and Fast/Slow Silicon), Wake-up latencies, energy savings, What would work even better? Q&A, Video demonstration silicon. Bio: Dr David Flynn, a Fellow in R&D at ARM Ltd, has been with the company since 1991, specializing in System-on-Chip IP deployment and methodology. He is the original architect behind ARM's synthesizable CPU family and the AMBA on-chip interconnect standard. His current research focus is low-power system-level design. He holds a BSc in Computer Science from Hatfield Polytechnic, UK and a Doctorate in Electronic Engineering from Loughborough University, UK. He is currently part-time Visiting Professor with the Electronics and Computer Science Department at Southampton University, UK. David is a primary author of the Low Power Methodology Manual co-developed with Synopsys and launched in 2007 and a contributing author to the VMM-LP launched 2009.
	Cavium Networks	YJ Kim, Senior Director, Embedded Processor Group. Designing & Delivering Powerful and Most Power Optimized Embedded Multi-core Processors. Abstract: Massive increases in network bandwidth and complexity are being driven by key new trends including secure cloud computing architectures, 4G mobile internet services, and IP video. These trends require next-generation multicore processor SoC's to deliver dramatically higher compute and services performance while maintaining very low power consumption and optimizing application performance per Watt to minimize the operating costs of datacenters, enterprise IT infrastructure, and service provider networks. Cavium Networks will present its strategy to addressing these challenges, highlighting an approach based on highly-efficient custom-designed general purpose 64-bit MIPS processor cores complemented by targeted hardware application acceleration for security, deep packet inspection, data compression/decompression and de-duplication, storage, and packet processing. Cavium will highlight how this approach is able to achieve up to a 10X+ improvement in performance per Watt vs. general-purpose solutions and will discuss how the same architecture and software can scale from very low-cost to the industry's highest-end performance range. Additional techniques for realtime dynamic power measurement will also be discussed. Example applications and application performance will also be reviewed. Bio: YJ Kim is Senior Director of the Embedded Processors Group at Cavium Networks since June, 2006. YJ has 20 years of experience in microprocessors. Prior to joining Cavium Networks, he held position as the General Manager of Intel Tolapai (IA SOC – EP80579), Product Marketing Manager of Intel Westport/IXP2350, co-founder/Director of API Networks, a company with $230M revenue in 2000, Marketing Director at Samsung Semiconductor, Inc and held various marketing positions at Intel x86 Microprocessor and FLASH groups. YJ holds B.S.E.E. and Master of Engineering in E.E. from Cornell University, and has attended Wharton Executive Program at University of Pennsylvania.
	UC San Diego	Houman Homayoun, National Science Foundation Computing Innovation Postdoctoral Fellow, UC San Diego. TBA. Abstract: TBA. Bio: Houman Homayoun received the PhD degree from the department of computer science at the University of California Irvine in 2010. He named a 2010 National Science Foundation Computing Innovation Fellow by the Computing Research Association (CRA) and the Computing Community Consortium (CCC). He was a recipient of the 4-years UC-Irvine computer science department chair fellowship. His research is on power-temperature and reliability-aware memory and processor design optimizations and spans the areas of computer architecture, circuit design and VLSI-CAD, where he has published more than 30 technical papers on the subject. His research is among the first in the field to address the importance of cross-layer power and temperature optimization in memory peripheral circuits. He received his BS degree in electrical engineering in 2003 from Sharif University of technology, Tehran, Iran. He received his MS degree in computer engineering in 2005 from University of Victoria, Canada.
	STMicroelectronics	Marcello Coppola, R&D Director. Spidergon STNoC: a cost effective technology for Green SoC. Abstract: Consumer electronics (CEs) is mainly characterized by its heterogeneity in products and markets. Moreover, large companies like Google, YouTube, Myspace, are revolutionizing the way to provide information contents. Today, several new CE devices have been introduced in the marketplace for receiving, visualizing, communicating, creating, and sending information. This changing implies that end-users are looking for devices with more features, better quality elegant and simple user interface and longer battery life. This trend has a big impact on the features that System-on-Chips (SoC) have to support and how those features have to be implemented to be power efficient. In this talk, we start to briefly introduce Spidergon STNoC technology. Spidergon STNoC is the ST Network on Chip, built on ST’s existing on-chip communications expertise while adding radical innovation derived from its research in Network-on-Chip (NoC) technologies. Today Spidergon STNoC technology is a configurable and extensible technology that provides an innovative on-chip communication network able to address all requirements of new demanding System-on-Chip (SoC) applications. Then, we will focus how the Spidergon low power services and the associate design EDA flow is able to deliver significant advantages to system designers in building green SoC by the inherent cost-effectiveness in term silicon area, wiring complexity and specific low power services. Finally some examples of Spidergon STNoC instances in real SoC are given to the audience. Bio: Marcello Coppola is working for STmicroelectronics, he is Head of the Grenoble Research Laboratory within “Advanced System Technology”, a corporate research organization in ST. He studied computer science at Pisa University. In 1992, he received his Laurea degree and started working at the Transputer architecture group of INMOS, Bristol (UK). For 2 and half years he worked on a research program regarding the architecture of the C104 router. His research interests include several aspects of design technologies for System on Chip, with particular emphasis to Network on Chip, MPSoC architecture, Programming Modeling and system level design. His publication record covers publications in the filed of simulation, modeling, SoC architecture and on-chip communication network. He wrote chapters for different books. He was one the members for the OSCI language working group. He contributed to SystemC2.0 language definition and OSCI standardization. He has chaired international conferences on SoC design and helped to organize several others. He is program committee member of DATE, FDL, CODES+ISSS, DAC. He is cited in Marquis “Who’s Who in Engineering” and IBC biographies.
	Micron Technology, Inc.	Jim Cooke, Sr. Manager, NAND Flash Marketing. A New Breed of NAND Flash Reduces Power and Simplifies Enterprise ASIC Designs. Abstract: NAND flash memory is not new to the enterprise storage market. However, traditional NAND flash can present significant design challenges for the ASIC designer. While good designers can address these challenges, solutions come at a price of longer design times and larger gate counts due to the increased complexity of the ASIC. In addition, a typical enterprise ASIC will can waste hundreds of signals to control an array of traditional NAND devices. Micron is offering a game changer with the development of a new class of NAND flash devices that are designed specifically for enterprise markets. These new devices will allow for more cost effective and higher performance ASIC’s by saving hundreds of signals and potentially millions of logic gates thereby reducing power. Bio: Jim Cooke is a Sr. Manager for Micron’s NAND Flash marketing team. He has a BSEE from the University of Massachusetts. Previously, he was responsible for managing the applications engineering group at Micron. Jim has held similar positions at Toshiba America Electronic Components. In addition, Jim has over 20 years of hands-on systems-level design experience in embedded applications and consumer markets.
	Virage Logic Synopsys	Mike Thompson, Director of Product Marketing for Processor and SoC Solutions. Effective Processing Solutions for Low-Power Heterogeneous Multiprocessing. Abstract: Use of Homogeneous multi-processing—multiple instances of the same CPU—in compute engines for servers and workstations began in the 1990’s. By the mid-2000’s, they began appearing in PCs and shipping in high-end consumer products. In the system on-chip arena, homogenous multiprocessing began to appear in the early part of this decade as a means of adding applications processors to offload the host. This was necessitated by increasing processing requirements appearing on embedded systems: phones that not only provided voice but also handled instant messaging, full web browsing, video and still camera, and even music playback. Other embedded applications likewise began adding on functions that demanded increasing computational performance: home-networking gear such as broadband gateways and Wi-Fi routers; storage controllers for hard drives and Flash-memory drives; digital TVs, Blu-ray Disc players, and set-top boxes; and ASICs for communications infrastructure and enterprise routers. The impetus to multiprocessing was the limitations encountered from simply increasing the clock rate of the host processor to handle the continuous flow of new functions being added to the processing task of these central hosts. The other compelling reason was to reduce the escalating power consumption and heat resulting from the increase in the clock frequency of the host processors. The simplest solution was to divide the growing workload into smaller tasks that could be handled by multiple processors that could be clocked at a lower frequency. To achieve real-time processing results architects started segregated tasks to improve predictability and performance. Early solutions saw collections of homogeneous processors shouldering the load—the solution was less than optimal since general purpose processors were not the most efficient at many specific tasks: for example floating point processing needed to control touch screen displays, or the signal processing essential for audio and video encoding and decoding. Over the past few years this has been changing. As the need for multiprocessing solutions has increased, the use of homogeneous collections of processors has given way to the use of the heterogeneous solutions that are common in most SoCs today. This is the result of all of the issues discussed previously, but power has been the biggest factor driving the use of heterogeneous architectures. This need for power control is being driven by two fundamental challenges encountered in building SoCs for today’s markets. That is, the need for long battery life in portable devices and the need to control heating in all electronic products. As we have followed Moore’s law down the process curve SoCs have become increasingly more complex, but with this complexity has come greater power dissipation. To control power dissipation and extend battery life clock frequencies have to be limited, so the solutions have to be optimized through the use of specialized processing engines that do more with fewer clocks. Ironically, it is also the move to more advanced processes that has enabled the use of these heterogeneous solutions that require more transistors to implement. That is, as transistors have become cheaper engineers are choosing to use more of them to implement heterogeneous solutions with specialized resources that limit maximum clock frequencies to control power consumption while doing the same or in many cases more work. A significant shift has occurred over the past ten years in the type and structure of the processing engines used on SoCs today. The homogeneous processor implementations used in the early part of this decade have given way to the use of specialized heterogeneous solutions to control power while continuing to address the ever increasing performance needs of the market. This trend will continue, enabling SoC designers to build the simplest to the most complex heterogeneous SoCs for their customers using a broad range of CPU IP, high speed memories and controllers, interface controllers and PHYs, as well as the design libraries that enable access to the latest 65, 40, and 28 nm process technologies. Bio: Mike Thompson is the Director of Product Marketing for Processor and SoC Solutions at Virage Logic where he is responsible for the development and infrastructure support of microprocessor cores and subsystem IP. Mike has more than 30 years experience in both design and support of microprocessors, microcontrollers, IP, and the development of embedded applications and tools working previously for Actel, MIPS, ZiLOG, Philips/Signetics, and AMD. He has a BSEE from Northern Illinois University and an MBA from Santa Clara University.
	5 Min Afternoon Break	5 Min Afternoon Break
	Panel (FREE for Everyone!)	“Technology & Entrepreneurship: Dreams, Realities & Opportunities” Open To Everyone
	UC Irvine STETINA BRUNDA GARRED & BRUCKER Excalibur Engineering Chapman University Brandman University Savant Company Inc.	Dr. Goran Matijasevic, Executive Director, Chief Executive Roundtable, UC Irvine. Moderator Bio: Goran Matijasevic is Director of Research Development at The Henry Samueli School of Engineering at UC Irvine. In this capacity, he works on formation of new industry-university and academic collaborations, especially focusing on new interdisciplinary research initiatives. Prior to this, he was the Research Coordinator of the Integrated Nanosystems Research Facility at UC Irvine, where he worked closely with industry partners on making them aware of available university resources. Prior to UCI, he worked as a senior engineer at QPlus, a telecommunications start-up company. From 1994 to 2001, he was at Ormet Technologies, where as Director of Research he was working on development of polymer and metal materials and structures for electrical interconnect of high density circuits, new metal alloys for use in conductive adhesives, materials for embedded passive components and heat sensors, and high thermal efficiency electronic substrates. ¨He managed multiple SBIR projects that led to several industry consortia projects, as well as a license agreement with a Fortune 100 company. He has 4 U.S. patents, 3 book chapters, and over 40 conference and journal publications and has served on the NEMI Industry Roadmap committee. He served as NanoWorld Conference Technical Chair, the Electronic Components and Technology Conference (ECTC) Interconnect Chair and Emerging Technologies Chair, the IEEE Sensors 2006 Local Chair, the ASME Frontiers in Biomedical Devices Co-Char, as well as on the LARTA Tech Transfer Conference Organizing Committee. He is currently on the OCTANe (Orange County Technology Action Network) Operations Committee and Vice Chair of OC Innovation. Goran received his PhD from UC Irvine in Electrical and Computer Engineering and his MBA from Pepperdine University. He is also a member of the TriTech Advisory Board, Southern California Biomedical Council Board, Tech Coast Venture Network, IEEE, and ASME. Panelist: 1. P. K. Shukla, Ph.D., CPIM, Vice Chancellor for Entrepreneurship, Director, Leatherby Center for Entrepreneurship and Business Ethics, Chapman University. 2. Eric Tanezaki, Intellectual Property Law Partner, Stetina Brunda Garred & Brucker. 3. Susan R. Jones, Managing Director, Corporate Finance Associates. 4. Joe Hayashi, Founding Partner, Fortis General Counsel. 5. Chris LaPlante, Founder/Owner, Excalibur Engineering. 6. TBA. This Panel Is Open To Everyone . . . Register for FREE Panel Pass More Updates Coming Soon . . . Several Opportunities to Win various Prizes During this Panel Discussion . . . Don't Miss Out!
	Stetina Brunda Garred & Brucker	Eric Tanezaki, Intellectual Property Law Partner, Stetina Brunda Garred & Brucker. Panelist Eric is a partner of Stetina Brunda Garred & Brucker, a boutique full service intellectual property law firm. He has represented numerous companies in various industries in relation to patent, trademark and copyright matters, seeking rights as well as related licensing. He received his undergraduate engineering degree from the University of Southern California, and his law degree from the McGeorge School of Law, University of the Pacific. Prior to law school Eric worked in the aerospace industry. Eric is the Executive Director of the Southern California Venture Network (SCVN.org). In addition, Eric is the IP Law Mentor to the USC Stevens Institute for Innovation.
	Chapman University	P. K. Shukla, Ph.D., CPIM, Vice Chancellor for Entrepreneurship, Director, Leatherby Center for Entrepreneurship and Business Ethics, Chapman University. Panelist EDr. Shukla received a Master’s of Science degree from the University of Southern California and his Ph. D. from the University of California, Los Angeles. Dr. Shukla has a total of six university degrees. He joined Chapman University in 1985 and is an Associate Professor of Management. He has edited two published textbooks and has presented/published several papers. His research focuses upon the application of managerial and strategic decision-making tools. Since 2006, he has served as Director of the Leatherby Center for Entrepreneurship and Business Ethics within the Argyros School of Business and Economics. Dr. Shukla has helped Chapman University students to win individual and team regional, national, and global awards/finalist rankings in Entrepreneurship & Business Plan Contests. The entrepreneurship program at Chapman University is ranked #6 among undergraduate programs and #8 among graduate programs nationally by The Princeton Review and Entrepreneur magazine out of 900 programs surveyed. Dr. Shukla received the 1st Place Best Faculty Advisor Award from Collegiate Entrepreneurs’ Organization in 2006 out of all global chapters. In 2008, he was selected to receive an Excellence in Entrepreneurship Education Teaching Award from ACTON Foundation for Entrepreneneurship Excellence to recognize the best entrepreneurship instructors nationally. He has served as a Curriculum Study Guide Developer and test writer for the “Economics and Entrepreneurship” section of the United States Academic Decathlon. Dr. Shukla has consulted with entrepreneurial firms at all stages--- business plan, inception, growth, succession planning, going public, and liquidation.
	Excalibur Engineering	Chris LaPlante, Founder/Owner, Excalibur Engineering. Panelist TBA.
		Open To Everyone Reception & Networking
		8th International SoC Conference Closed.