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8th International System-on-Chip
(SoC)
Conference, Exhibit & Workshops
November 3 & 4, 2010
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Hilton Irvine/Orange County Airport, Southern California
The Most Informative &
Targeted
SoC, ASIC, FPGA, ASSP, and Foundry
Technology Conference & Exhibit of the Year
Don't Miss Out! |
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If you
have any questions or need more information, please contact:
SoC@SavantCompany.com
or
949-851-1714
Thank
you!
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IBM
Keynote
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Dr.
J. Antonio Carballo, WW Manager, IBM Microelectronics Services,
Semiconductor Partner, IBM VC Group.
Bio:
Juan-Antonio Carballo is IBM Corporation's Venture Capital Executive for
Semiconductors and Hardware Systems, responsible for creating and managing
strategic projects with top-tier Venture Capital firms and their portfolio
companies. Prior to this role, Juan-Antonio was leading research in adaptive
communications chips at IBM Research. He won an IBM Research Division award
for his work in this area. He filed 23 patents and has over 20 publications
in low-power design, communications systems, design economics, and
electronic design management. He is the Chair of the International
Technology Roadmap for Semiconductors (ITRS) Design and System Drivers
Chapters, the Chair Elect of IEEE's DATC Committee, and VSIA's R&D Chair in
2004-5. He has been on the committee of six symposiums and conferences, and
was the General Chair for Electronic Design Processes
2004 in Monterey, CA. His prior work experience includes stays at Digital
Equipment (currently HP) and LSI Logic. Juan-Antonio holds a Ph.D. in
Electrical Engineering from the University of Michigan, an M.B.A. from the
College des Ingenieurs (Paris), and a M.Sc. in Telecommunications Engineering
from the Universidad Politecnica de Madrid.
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Freescale
Keynote |
Ken
Hansen, Sr. Fellow, Vice President and Chief Technology Officer (CTO),
Freescale.
TBA
Abstract: TBA
Bio: Ken Hansen is sr. fellow, vice president and chief technology officer
with Freescale Semiconductor. Prior to becoming CTO, Ken was vice president
in the chief development office where he focused on improving design
efficiency and reducing product cost across all the Freescale businesses.
Previously, he held several senior technology and management positions at
Freescale and Motorola leading research and development teams.
He received his BSEE and MSEE from the University of Illinois, is a Senior
Member of the IEEE, and holds 12 U.S. patents. Ken is an industry veteran,
with 33 years of analog and digital design experience in bipolar, CMOS, and
BiCMOS technologies primarily in the area of wireless communications.
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Technical University of
Valencia
(Spain)
Keynote
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Dr.
Jose Duato, Professor of Computer Architecture and Technology, Technical
University of Valencia (Spain),
"Beyond the Power and Memory
Walls: The Role of NoCs in Future System Architectures."
Abstract: Although most
research on NoCs has assumed the use ofregular topologies like 2D meshes,
some current trends in chip architecture, combined with expected technology
limitations and usage models, will very likely oblige designers to consider
less regular topologies to provide the best cost-performance trade-off.
Moreover, the set of nodes interconnected by those NoCs will also be
heterogeneous, including computational cores of different sizes and
computing power, cache blocks and local stores, accelerators of different
kinds, and memory controllers. The memory wall problem will likely be
addressed by using 3D integration, which will increase heterogeneity
significantly, due to the need for locating the hottest cores in the top
layer.
Therefore, in order to deliver the best cost-performance trade-off while
minimizing resource and power consumption and providing the maximum
flexibility, heterogeneity needs appropriate hardware support in the NoC.
This talk motivates the need for efficiently supporting heterogeneity, and
sketches some results along this direction, describing power-efficient
routing algorithms that provide support for multiple heterogeneous, possibly
overlapping regions (e.g. virtual machines, coherence domains) in the
presence of faulty components. The talk also shows how a hierarchical
interconnect (on-chip, on-substrate) can significantly shorten design cost
and time to market.
Bio: Jose Duato received the
MS and PhD degrees in electrical engineering from the Technical University
of Valencia, Spain, in 1981 and 1985, respectively. Currently, Dr. Duato is
Professor in the Department of Computer Engineering (DISCA) at the same
university. He was also an adjunct professor in the Department of Computer
and Information Science, The Ohio State University.
His current research interests include interconnection networks and
multiprocessor architectures. Prof. Duato has published over 400 refereed
papers. He proposed a powerful theory of deadlock-free adaptive routing for
wormhole networks. Versions of this theory have been used in the design of
the routing algorithms for the MIT Reliable Router, the Cray T3E
supercomputer, the on-chip router of the Alpha 21364 microprocessor, and the
IBM BlueGene/L supercomputer. Prof. Duato also developed RECN, the only
truly scalable congestion management technique proposed to date, and a very
efficient routing algorithm for fat trees that has been incorporated into
Sun Microsystem's 3456-port InfiniBand Magnum switch. Currently, Prof. Duato
leads the Advanced Technology Group in the HyperTransport Consortium, which
developed the High Node Count HyperTransport Specification 1.0 to extend the
device addressing capabilities of HyperTransport in several orders of
magnitude.
Prof. Duato is the first author of the book "Interconnection Networks:
An Engineering Approach". Dr. Duato served as a member of the editorial
boards of IEEE Transactions on Parallel and Distributed Systems, IEEE
Transactions on Computers, and IEEE Computer Architecture Letters. He has
been the General Co-Chair for the 2001 International Conference on Parallel
Processing, the Program Committee Chair for the Tenth International
Symposium on High Performance Computer Architecture (HPCA-10), and the
Program Co-Chair for the 2005 International Conference on Parallel
Processing. Also, he served as Co-Chair, member of the Steering Committee,
Vice-Chair, or member of the Program Committee in more than 60 conferences,
including the most prestigious conferences in his area (HPCA, ISCA, IPPS/SPDP,
IPDPS, ICPP, ICDCS, Europar, HiPC).
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Four Informative &
Enlightening Panel Discussions
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Panel 1: Exploring Opportunities for the Integration of Silicon
and Biotechnology. Wed, Nov 4.
Moderator: Mark A. Miller, V.P. Business Development, X-Fab
Semiconductor Foundries.
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Panel 3:
Green Chips: Technology, Trends, and Challenges in
Low-Power Multicore SoC Designs. Thu, Nov 5.
Moderator: Steve
Leibson, Principal at S Leibson Consulting, Contributing Editor at EDN
Magazine. |
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Panel 2: Improving Design Productivity and IP Quality through the
Effective Use of Standards for Complex Multicore SoCs. Wed, Nov 4.
Moderator: Dr. Juan-Antonio Carballo, WW Manager, IBM
Microelectronics Services, Semiconductor Partner, IBM VC Group. |
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Panel 4: Entrepreneurship & Technology: Dreams, Realities &
Opportunities. Thu, Nov 5.
Moderator: Dr. Goran Matijasevic is Director of Research
Development at The Henry Samueli School of Engineering at UC Irvine.
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Worldwide Rights Reserved.
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