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5th International
System-on-Chip (SoC)
Conference, Exhibit &
Workshops
November 7 & 8, 2007
—
Radisson Hotel Newport Beach, Southern California
The Most Informative, Targeted, and Affordably
Priced
SoC, ASIC, ASSP, FPGA, and Foundry Technology Conference &
Exhibit Event of the Year!
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Conference Program Abstracts &
Bios* |
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8:00 -
8:15
Savant
Company Inc. |
Farhad
Mafie, President and CEO of Savant Company Inc.
"Welcome and Opening Remarks, Technology/Market Trends."
Farhad
has over 20
years of experience in semiconductor and computer businesses and more than 10
years of university-level teaching experience. Farhad is the former
Vice President of Marketing/Business Development and Technical Sales Engineering at
Toshiba America Electronic Components, Inc. He was responsible for marketing
the entire Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth,
Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.).
He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer
products & solutions based on ASSP and SoC Models.
Farhad established Toshiba's on-line
Tech-Support System as well as Toshiba's on-line System Solution Selling
methodologies for all Toshiba's products in the North American markets.
These on-line systems were adopted by Toshiba on a worldwide basis. He
also developed Toshiba's ASSP Business Unit and Technical Sales Engineering
Team as two brand new organizations for the company. Farhad has also worked at Lucent Technologies
on marketing communications ICs,
Toshiba Information Systems on product definition for Toshiba's notebooks
and handheld products, Unisys on designing new processors and computer
systems, and MSI Data on
designing data collection products. He has a Master of Science and a
Bachelor of Science degree in Electronic Engineering from California State
University, Fullerton. His combined business and academic experience
has given Farhad a unique ability to effectively communicate complex new
technologies to business professionals at all levels, as well as the ability
to foresee emerging leading-edge technologies.
Farhad is an author and a
translator, and he writes articles for a variety of journals and Web-based
magazines on technology and political affairs.
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8:15 am - 12:00 am |
Semiconductor Technology & Trends:
New Design
Approaches for Complex SoCs
Track
Chairman: Dr. Goran Matijasevic is Director of Research Development at The
Henry Samueli School of Engineering at UC Irvine |
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Dr. Goran Matijasevic is Director of Research
Development at The Henry Samueli School of Engineering at UC Irvine
Bio:
Goran Matijasevic is Director of Research Development at The Henry Samueli
School of Engineering at UC Irvine. In this capacity, he works on formation
of new industry-university and academic collaborations, especially focusing
on new interdisciplinary research initiatives. Prior to this, he was the
Research Coordinator of the Integrated Nanosystems Research Facility at UC
Irvine, where he worked closely with industry partners on making them aware
of available university resources. Prior to UCI, he worked as a senior
engineer at QPlus, a telecommunications start-up company. From 1994 to 2001,
he was at Ormet Technologies, where as Director of Research he was working
on development of polymer and metal materials and structures for electrical
interconnect of high density circuits, new metal alloys for use in
conductive adhesives, materials for embedded passive components and heat
sensors, and high thermal efficiency electronic substrates. ¨He managed
multiple SBIR projects that led to several industry consortia projects, as
well as a license agreement with a Fortune 100 company. He has 4 U.S.
patents, 3 book chapters, and over 40 conference and journal publications
and has served on the NEMI Industry Roadmap committee. He served as
NanoWorld Conference Technical Chair, the Electronic Components and
Technology Conference (ECTC) Interconnect Chair and Emerging Technologies
Chair, the IEEE Sensors 2006 Local Chair, the ASME Frontiers in Biomedical
Devices Co-Char, as well as on the LARTA Tech Transfer Conference Organizing
Committee. He is currently on the OCTANe (Orange County Technology Action
Network) Operations Committee and Vice Chair of OC Innovation. Goran
received his PhD from UC Irvine in Electrical and Computer Engineering and
his MBA from Pepperdine University. He is also a member of the TriTech
Advisory Board, Southern California Biomedical Council Board, Tech Coast
Venture Network, IEEE, and ASME. |
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8:15 - 8:45
iSuppli |
Jordan Selburn,
Principal Analyst, Core Silicon, iSuppli Corp
Bio: Jordan
came to iSuppli with decades of extensive experience in ASIC, programmable
logic and semiconductor intellectual property (IP) analysis, product
marketing, and engineering development.
Prior to joining iSuppli, Jordan served as the Director of Product Marketing
for Amphion Semiconductor, where he was tasked with managing the
technical product marketing team. He launched products in all of Amphion’s
product families in addition to providing in-depth sales support for the
products and the IP business model. Prior to his tenure with Amphion, Jordan
was the Principal Analyst for ASIC and IP at Gartner Group/Dataquest and as
such was responsible for the evaluation and analysis of semiconductor IP as
well as the ASIC and programmable logic markets. He formulated and presented
tracking and forecasting on technology and market trends with particular
emphasis on system-level integration as part of his duties at Gartner
Group/Dataquest.
Marketing Manager and Product Line Manager positions at LSI Logic preceded
his employment at Gartner Group/Dataquest. At LSI Logic, Jordan was charged
with establishing product positioning and pricing for their production ASIC
products. In addition, he generated technical requirements and provided
marketing direction to product development teams along with creating
business plans for 0.6 micron and 0.35 micron technologies. Before LSI
Logic, Jordan was an ASIC Technology Manager and a Corporate Applications
Engineer at Valid Logic Systems/Cadence Design Systems and was also
associated with Agilent/EEsof, Inc., and Harris Corporation in various
engineering capacities.
Jordan holds a Master of Science in Engineering Economic Systems from
Stanford University in addition to an MBA with distinction from Santa Clara
University and a BSEE with honors from the University of Michigan. |
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8:45 - 9:15
Fujitsu |
Ray
Abrishami, Senior Director of Wireless Business Group, Fujitsu
Microelectronics America, Inc.
"SoC for Mobile WiMAX"
WiMAX is fast becoming the Internet technology of choice for
a vast array of applications involving simultaneous data, voice and video
communications. This technology is characterized by its superior throughput,
range, and quality of service. A key challenge facing all communication
technologies is how to deliver the promised capabilities and services cost
effectively. WiMAX technology is setting out to achieve cost effectiveness
in an unprecedented way. SoC class of technologies place at the very center
of Mobile WiMAX global deployments offering exceptional integration of
capabilities and services, portability, very low power consumption, and
remarkably high performance. Fujitsu has outlined a very impressive WiMAX
product roadmap consisting of a series of SoC solutions to address specific
target application areas. Fujitsu’s vertically integrated semiconductor
products sector is able to bring together circuit, IP, design methodology,
design libraries, packaging technologies on a platform of a highly scaled
COMS technology to address the mobile WiMAX requirements. The complete
solution is supported with highly optimized system and media access control
SW. An example of our product roadmap is a highly integrated, one-chip
mobile baseband SoC, which uses 90nm low-leakage process technology,
well-suited for PC cards and other media-rich mobile applications. The
mixed-signal SoC has achieved an 18.6Mbps transfer rate in sample
installations and lab demonstrations at substantially below 500 mW of power
dissipation.
Bio: Ray Abrishami is currently the Senior Director of
SoC Engineering and Marketing at Fujitsu Microelectronics America, Inc. (FMA).
His responsibilities include product marketing for FMA and SoC development
for specific vertical markets such as WiMAX-compliant broadband wireless,
VoIP and biometric sensor products. He also oversees the development of FMA
solution platforms for SoC involving IP development, acquisition and
integration with processor cores and peripheral sub-systems as part of the
IPWare™ SoC program. Before joining Fujitsu, Abrishami worked at LSI Logic
Corporation where he held various senior engineering management positions in
the ASIC Division. His responsibilities included design methodology
development, cell architecture, circuit design and design library
development functions. He also had engineering management responsibility for
the development and delivery of several generations of sub-micron technology
products. Abrishami has been closely involved in the definition and
development of SoC, intellectual property, top-down VLSI design
methodologies and automation tools in the areas of front-end design,
physical design and test/testability. Prior to joining LSI Logic, Abrishami
held the highest-level engineering and general management positions at Data
General Corporation‘s Semiconductor Division where he directed the VLSI
system development groups. He led the development and release of VLSI chip
sets for three generations of computer systems. Abrishami represented LSI in
the Semiconductor Research Corporation’s (SRC) Design Sciences Technical
Advisory Board. He was chairman of SRC's Design Sciences Technical Advisory
Board in 1996. From 1994-1997, Abrishami was also a member of the Design and
Test Technical Working Group (TWG), responsible for the development of the
National Technology Roadmap for Semiconductors. Abrishami holds bachelor’s
and master’s degrees in electrical engineering from San Jose State
University. He participated in Stanford University’s engineering management
program, and is a member of IEEE, Tau Beta Pi and Eta Kappa Nu. He has been
granted three U.S. patents in circuits and systems.
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9:15 - 9:45
Broadcom |
Dr. Hooman T. Parizi,
Principal IC Design Scientist, Broadcom Corporation.
"Power, Performance, and
Programmability requirements for Wireless Application SoCs."
The increasing number of
wireless communication standards creates new demands for their platform
architectures. In addition to fulfilling high data rate, low cost and low
power consumption requirements, they also need to be flexible enough to
support multiple standards in a multimode radio system. Traditional Digital
Signal Processors (DSPs) cannot provide the target performance for wireless
systems. On the other hand, Application Specific Integrated Circuits (ASICs)
are the favorite solution for wireless systems. ASIC are fast and consume
low power, but they are vulnerable to changes. Even changing small features
in ASICs requires repeating most of the design and fabrication process,
which is expensive and increases the time to market for these systems. The
future growth and development of System on Chip (SOC) technologies for
wireless communication systems relies on the longer life cycle of new
products. The current approach of integrating ASIC solutions is not
economically attractive for the new generation of SOC chips, because of all
the nonrecurring expenses (NRE) such as mask, engineering, validation, and
the shorter life cycle of the product.
Demands for programmability as well as power and performance have made
reconfigurable architectures an attractive alternative solution for wireless
systems platforms. In this talk HERS, a Heterogeneous Reconfigurable System
is introduced as a platform for wireless communication systems. HERS is a
set of reconfigurable engines connected through a general high speed bus.
Each reconfigurable engine is a specialized reconfigurable architecture for
a category of similar algorithms. As each family of algorithms has a limited
set of flexibility requirements, their reconfigurable engine platforms can
be highly optimized for power and performance. HERS is an optimal solution
in terms of power, programmability and performance.
Bio: Hooman T. Parizi is Principal IC Design Scientist at Broadcom
Corporation working on design and architecture of high speed DSP chips in
DSM technologies. Before joining Broadcom he was with Morpho Technologies, a
start up specialized in Reconfigurable DSP architecture and design.
He holds a PHD degree from university of California at Irvine and is the
co-author of more than ten papers. His interest is in Computer Architecture,
Reconfigurable Computing, Design Automation, and VLSI implementation of DSP
algorithms.
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9:45 - 10:00
Morning Break
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Morning Break |
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10:00 - 10:30
Keynote
Jazz Semiconductor |
Dr. Marco Racanelli, Vice
President of Technology and Engineering, Jazz Semiconductor.
Keynote
Dr. Marco Racanelli is the
Vice President of Technology and Engineering at Jazz Semiconductor, an
independent pure-play wafer foundry focused primarily on specialty CMOS
process technologies optimized for the manufacture of highly integrated
analog and mixed-signal semiconductor devices. His responsibilities include
leading technology development, modeling, design automation and design
service teams. Before joining Jazz in 2002, Dr. Racanelli held
technology and engineering positions at Conexant Systems. He also held
management positions with Rockwell Semiconductor Systems prior to the
Conexant spin-off in January 1999. He joined Rockwell in 1996 and has since
held several posts of increasing responsibility in the area of technology
development. In these positions, Dr. Racanelli helped establish
industry leadership in SiGe and BiCMOS technology, and was instrumental in
building a strong design support organization for Jazz Semiconductor. Prior
to joining Rockwell, Dr. Racanelli worked at Motorola, Inc., where he
contributed to bipolar, SiGe and SOI development for Motorola’s
Semiconductor Products Sector. He has authored or co-authored more than 50
technical publications and holds 30 U.S. patents. Dr. Racanelli
received his Ph.D. and M.S. degrees in Electrical and Computer Engineering
from Carnegie Mellon University, and his B.S. degree in Electrical
Engineering from Lehigh University.
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10:30 - 11:00
IBM |
Al Yanes, Distinguished
Engineer, IBM Systems and Technology Group.
"Power 6 South Bridge."
Bio: Al
Yanes is a Distinguished Engineer in the IBM Systems and Technology Group.
He is a member of the Technology Collaboration Services delivery team. He is
known throughout IBM as the leader in Peripheral Component Interface (PCI),
PCI-X and PCI Express hardware technologies and a key contributor to the
development of the PCI-X and PCI Express specification through his work as
chair of the PCI-SIG industry standardization committee. He brings more than
20 years of direct experience in the development of Input/Output (I/O)
technologies, storage controllers, System i and p and high-end System x
servers. Al is an expert in I/O and system hardware architecture, logic
design, hardware verification, timing closure, hardware bringup and
validation. He is a Master Inventor with 25 patents in I/O technologies. Al
joined IBM in 1985 in Tucson, Ariz. working on storage controllers. He
continued his storage controller work in San Jose in 1993 and eventually
moved to Rochester in 1996 to work on System i PCI bridge chips. Al holds a
bachelor in science in computer engineering from Rensselaer
Polytechnic Institute. |
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11:00 - 11:30
Tower
Semiconductor |
Rafi Nave, CTO, Tower
Semiconductor.
"Specialized Foundries Bring
Distinct Business and Technical Advantages to Chip Companies"
Chip companies that are looking for customized business solutions in order
to maximize their long-term, reliable performance, are coming to realize the
distinct business and technical advantages of working with specialized
foundries.
The foundry market is dominated by a few large players; however, independent
specialty foundries have a distinct advantage in being able to deliver
highly customized solutions to the chip companies they partner with. Many of
the larger foundries won't even bother offering specialized chip design or
device solutions below certain quantity thresholds. Needless to say, the
market for specialized IC at modest quantities is significant. In addition,
specialized foundries also offer an additional advantage by allowing chip
companies to increase their supply-chain security. Partnering with a smaller
specialized foundry allows chip companies to diversify their production and
optimize their time to market, cost and products performance through
tailor-made solutions.
Bio:
Tower Semiconductor CTO Rafi Nave can address the potential of the
specialized foundry business model and discuss the methods that specialty
foundries must implement in order to compete in the marketplace. Specialty
foundries must expand their production offerings, focusing on dedicated
customer service, as well as offer value-adds such as design support and
customized business solutions to help customers sustain long-term, reliable
performance, while delivering on-time and on-budget results. |
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11:30 - 12:00
Grandis |
Farhad
Tabrizi, Chief Executive Officer and President
Embedded Memory Using Spin-Transfer Torque RAM (STT-RAM).
Spin-Transfer Torque RAM (STT-RAM™)
is an emerging memory technology having all the characteristics of an ideal
memory “universal memory” and represents a breakthrough over
first-generation, field-switched magnetic random access memory (MRAM)
technology. STT-RAM’s unique synthesis of non-volatility, fast read and
write speed, unlimited endurance, and excellent scalability, provides
significant advantages over conventional memory technologies and offers
system designers the ability to develop new products with high performance,
low power consumption and low cost. In this talk, I will present
embedded STT-RAM solutions for SoC applications. eSTT-RAM has key
performance and cost advantages for replacing eSRAM, eFlash and eDRAM.
Farhad Tabrizi is president
and chief executive officer of Grandis, Inc. In January 2007, he was
appointed to this position, succeeding William Almon, Grandis co-founder,
who remains a major shareholder. Tabrizi joined the company from Lexar
Media, Inc., where he served as vice president, supply chain management and
corporate development. Previously, he was vice president of worldwide
marketing for Hynix Semiconductor. In this position, he focused on
developing, marketing and supporting Hynix's strategies for growing the
corporation's DRAM and flash businesses. Prior to joining Hynix, he held
various management and design positions at leading semiconductor companies.
Tabrizi brings to Grandis over 23 years experience in senior management,
design, marketing, supply chain management, business development, strategic
alliances, and industry standard committee chairmanship in the electronics
industry. He received his Master of Science degree in Electrical Engineering
from the University of California at Davis. |
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11:30 - 12:00
Lunch |
Lunch |
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1:00 – 1:30
Keynote
Intel |
Dr.
Jeff Parkhurst, Academic Research Programs Manager in the Design Sciences
Area.
Keynote:
Moore’s Law and Tera-scale computing: Future SoC Trends for
Complex Designs.
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Multicore,
CPUs, DSPs & NoCs for Complex SoCs
Track
Chairman: TBD |
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1:30 ‒ 2:00
Tensilica |
Steve
Leibson, Technology Evangelist, Tensilica Corporation.
"Component-Level Multimedia Function Blocks for Mobile SoC Designs."
This presentation provides the SOC designer and design manager with the
technical details they need to incorporate digital multimedia codecs into
their designs without first becoming codec experts. Such black-box design
capabilities are increasingly important in a world of rapidly changing
multimedia compression standards and constantly shrinking design schedules.
Although video encoding and decoding are complex processes, Tensilica’s
family of preconfigured Diamond Audio and Video Engines simplifies the task
for an SOC design team by acting as low-power black boxes that SOC designers
can incorporate into their portable multimedia and handset chips without
becoming H.264/AVC, MPEG-4, and digital-audio experts. Both the
Diamond Video Engine and the Diamond Audio Engine, which is currently in
volume production inside of multimedia and mobile-phone handset SOCs,
illustrate how processors and ready-to-run firmware can form the core of a
complex, high-performance, low-power IP block. None of the Diamond
Audio and Video Engine’s internal operations are visible to the host
processor, which is consistent with the IP blocks’
role as component-level SOC building blocks. Hardware designs incorporating
Tensilica’s Diamond Audio and Video Engines are not complex. The engines,
like the other system components, attach to the main system bus. In some
designs, the Diamond HiFi 2 Audio Engine can also serve as the host
processor. Predefined sets of API calls operate the Diamond Audio and
Video Engines. The Diamond HiFi 2 Audio Engine’s software library includes a
wide range of ready-to-run digital-audio codecs and, similarly, the Diamond
Video Engine has a library of video codecs. Using this block-oriented
approach to design, SOC development teams can rapidly assemble extremely
complicated SOCs from complex, proven IP cores and then program these SOCs
with application code to produce unique products for the market.
Bio: Steve Leibson is an experienced hardware and software design
engineer, engineering manager, and design consultant. He spent 10 years
working at electronic systems companies including HP’s Desktop Computer
Division, Auto-Trol Technology (graphics workstations), and Cadnetix (EDA
workstations) after earning his BSEE cum laude from Case Western Reserve
University. At HP, Auto-Trol, and Cadnetix, he specialized in the design of
desktop computers and workstations, especially in the areas of system and
I/O design. He then spent 15 years as an award-winning technology
journalist, publishing more than 200 articles in Microprocessor Report, EDN,
EE Times, Electronic News, and the Embedded Developers Journal. He served as
Editor in Chief of both EDN and the Microprocessor Report and was the
founding Editor in Chief of the Embedded Developers Journal. Leibson has
just written and published “Designing SOCs with Configured Cores,” a
treatise on 21st-century MPSOC design. Twenty years earlier, he wrote and
published “The Handbook of Microcomputer Interfacing,” which was published
in English, French, and Dutch, and was used as a university textbook for
many years. In 2004, he co-authored “Engineering the Complex SOC” with
Tensilica’s president and CEO Chris Rowen, which has also been used as a
textbook in university classes. He has also contributed chapters to several
other SOC design books since joining Tensilica in 2001. |
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2:00 ‒ 2:30
ARM |
Dr. Robert C.
Aitken, Fellow, R&D, ARM Corporation.
Bio: Robert C. Aitken
is an R&D Fellow at ARM. His areas of responsibility include library
architecture, low power design, and design for manufacturability. He has
given tutorials and short courses on several subjects at conferences and
universities worldwide. He has published over 50 technical papers, and holds
a Ph.D. degree from McGill University in Canada. |
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2:30 ‒ 3:00
MIPS
Technologies |
Kevin D. Kissell, Principal Architect,
MIPS Technologies,
"Considerations
in Selecting Multicore and Multi-threaded Implementations."
Abstract:
Traditional frequency scaling is becoming less and less economical in
today’s SoC designs. Deeper pipelines require more logic, area, power to
achieve higher frequencies in a given process. Multicore and multi-threaded
designs offer viable alternatives for applications with suitable software
models. But should you choose multi-threaded CPUs, multiple independent
cores or even multiple multi-threaded cores? The solution depends on the
application. This presentation will discuss the considerations for
selecting the best solution, including flexibility, cache, task coordination
and partitioning requirements, predictability of CPU requirements, hardware
and software complexity, data sharing patterns, and cost/performance models.
It will also include discussions of symmetric multi processing (SMP) and
coherent multiprocessing (CMP) systems.
Bio: Kevin D. Kissell is principal
architect at MIPS Technologies, and has been a part of the MIPS architecture
development team since 1997. He was first involved in the architecture and
design of RISC microprocessors when he joined the original Fairchild Clipper
design team in 1983. In between, Kevin has been variously responsible for
processor, systems and software architecture, for decoupled access/execute
supercomputers at ACRI, massively parallel distributed memory computers at
nCUBE, and large-scale shared-memory supercomputers at Evans & Sutherland.
His work at MIPS includes having been principal architect of the MIPS MT
multi-threading architecture and the SmartMIPS™ extensions for smart cards.
He holds a degree in computer science from the University of California at
Berkeley.
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3:00 - 3:15
Afternoon
Break |
Afternoon Break |
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3:15 - 3:45
Texas
Instruments |
Dr. Thanh
Tran, Embedded Hardware Systems Manager,
Texas
Instruments, Inc.
“Scalable Video Platform Enabling HD Video Communication.”
As the migration to high-definition (HD) video communication picks up speed,
video-system designers are faced with new challenges related to bandwidth
requirements, image quality, and low latency video CODEC flexibility. In
this presentation, we are showing the scalable video platform design using
multiple TI Digital Media processors that is capable of doing HD encode,
decode and transcode simultaneously. This is an ideal platform for video
communication and infrastructure applications.
Bio:
Dr. Thanh Tran has extensive experience in audio, video, computer and
communication systems design and is the Infrastructure Video Systems Manger
at Texas Instruments Incorporated. At TI, he is leading a hardware/software
systems team to develop reference designs and frameworks for high speed DSP/SOCs.
He has held other senior design positions at Compaq Computer, ReplayTV,
Eagle Wireless Incorporated, Bose Corporation and Zenith Electronics
Corporation. Tran is an IEEE Senior member and currently serves on the IEEE
System-On-Chip (SOCC) Organizing Committee as the Technical Program Chair,
and the IEEE International Conference on Consumer Electronics (ICCE) as the
Technical Program Committee member. He has published over 17 technical
papers and current holds 20 issued patents related to designs of video,
audio, computer and communication systems. Here is a partial list of Dr.
Tran’s recent accomplishments.
• Leading a hardware and software systems team to develop the next
generation scalable HD video platform.
• Led a team to create and productize the low cost and high performance
video SOCs, DM643x.
• Led a team to productize the Davinci video platform, DM644x. This includes
DDR, video and audio designs.
• Led a team to productize the C6455 1GHz device. This includes DDR2 533 and
multi-gigahertz SRIO designs.
Tran’s doctoral research, gated direct sequence spread spectrum clock
distribution system, led to three patents pending and one startup company,
X-EMI, in Austin, Texas. He is currently an adjunct faculty member at Rice
University where he is teaching audio and video and embedded systems
designs. Tran received a BSEE degree from the University of Illinois at
Urbana-Champaign, Illinois and Master of Electrical Engineering and Ph.D. in
Electrical Engineering degrees from the University of Houston, Houston,
Texas.
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3:45 - 4:15
ST
Microelectronics |
Antonio-Marcello
Coppola, Head of the Grenoble Research Laboratory, ST Microelectronics.
"ST NoC: The Next
Generation On Chip Communication Architecture for Consumer Applications."
Market, application and technology trends lead to new challenges for the
on-chip
Interconnections: a packet-switched on-chip micro-network (called in
literature Network on Chip) is foreseen to be the natural evolution of the
current bus-based solution, for overcoming its lack in scalability,
performance, power consumption and reliability. In this presentation we will
present the low cost, high performance STBUS evolution, called Spidergon
STNoC (S-STNoC). S-STNoC, based on a scalable, regular, point-to-point
topology combined with low complexity hardware, is bringing more performance
and less area/power compared to standard busses.
Bio: Marcello Coppola is working for STmicroelectronics, he is Head
of the Grenoble Research Laboratory within “Advanced System Technology”, a
corporate research organization in ST. He studied computer science at Pisa
University. In 1992, he received his Laurea degree and started working at
the Transputer architecture group of INMOS, Bristol (UK). For 2 and half
years he worked on a research program regarding the architecture of the C104
router.
His research interests include several aspects of design technologies for
System on Chip, with particular emphasis to Network on Chip, MPSoC
architecture, Programming Modeling and system level design. His publication
record covers publications in the filed of simulation, modeling, SoC
architecture and on-chip communication network. He wrote chapters for
different books. He was one the members for the OSCI language working group.
He contributed to SystemC2.0 language definition and OSCI standardization.
He has chaired international conferences on SoC design and helped to
organize several others. He is program committee member of DATE, FDL,
CODES+ISSS, DAC. He is cited in Marquis “Who’s Who in Engineering” and IBC
biographies. |
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4:15 - 4:45
NXP
Semiconductors |
Selliah
Rathnam, Fellow, NXP Semiconductors
"Nano-scale SoCs for Connected
Consumer Application."
The ongoing trend toward nano-scale
CMOS SoC integration is essential for the connected consumer; however, it
creates challenges due to new device characteristics and the complexity
resulting from the high number of functions in one die. In this talk, we
will illustrate how NXP Semiconductors addresses the requirements for the
connected consumer, including low power, vibrant media capabilities,
multi-standard communication pipes and consumer price points.
Bio: Selliah Rathnam is
a Fellow at NXP Semiconductors, based in San Jose, California. He is
responsible for the strategic direction of NXP’s System-on-Chip (SOC)
infrastructure technologies, ensuring the company’s SOC solutions continue
to meet and exceed customer expectations. Over the course of his ten year
career at NXP, formerly Philips Semiconductors, Selliah held a variety of
positions relating to SOC architecture and products, including: chief SOC
architect for SOC products for digital TV applications; architect for VLIW-Based
Trimedia CPU Projects; and architecture group manager for Digital TV SOC
products. Prior to Philips Semiconductors, Selliah served as senior director
of architecture of Silicon Access Networks. He also worked at Sun
Microsystems for seven years, participating in various reduced instruction
set computer (RISC) CPU projects and a Very Long Instruction Word (VLIW)-based
CPU research project. Selliah graduated with a Master of Science in
computer science from Texas Tech University, and obtained a Bachelor of
Science in electronics and communication engineering from the University of
Madras, India. He is currently pursuing a Master of Business Administration
at Santa Clara University.
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4:45 - 5:15
Texas A&M
University |
Praveen
Bhojwani, Texas A&M University
Bio: Praveen Bhojwani
is a PhD candidate of Computer Engineering at Texas A&M University, College
Station, TX. He received his MS in Computer Engineering from Texas A&M
University in 2003 and his B. Tech (Honors) in Computer Science &
Engineering from the Indian Institute of Technology (IIT), Kharagpur, India
in 2001. Praveen’s research area has primarily been in the domain of
networks-on-chip (NoC). He has published a number of papers identifying
important design issues in NoC-based design. His research interests also
include power-aware system design, computer architecture and design
verification. |
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Panel |
Panel:
“Emerging Trends for Complex SoCs: From Advanced
Multicore/CPUs/DSPs To Innovative Embedded Memories”
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5:15 - 6:15
EDN
Novelics
MIPS
NVIDIA
BDTI
Tensilica
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Maury Wright, Editorial Director, EDN Worldwide
Moderator
Maury Wright is Editorial
Director of EDN Worldwide, which includes EDN magazine and EDN.com (the
Internet home of EDN, Electronic News, and Electronic Business).
Maury graduated from Auburn University in 1978 with a BSEE and a curriculum
emphasis on digital design and development with early microprocessors.
Subsequently, he took graduate-level courses at Auburn and San Diego State
University with an emphasis on microprocessors and digital-signal
processing.
Maury's engineering experience includes stints at San Diego-based General
Dynamics Convair division and The Computation Company. At General Dynamics,
he worked designing ground support equipment for the Tomahawk cruise
missile. At Computation, he worked on early microprocessor-based office
systems and on ophthalmic instruments based on microprocessors.
Maury first joined EDN in 1983. During his career, he has worked in several
capacities at EDN and was also the founding editor of CommVerge magazine
(may it rest in peace). Maury has specialized in covering computers and
peripherals, with emphasis on enabling technologies in the multimedia area
and voice/data/video convergence.
As editorial director, Maury spends time in EDN's offices in San Jose and
Waltham, Mass., as well as his home office near San Diego.
1:
Dr. Cyrus Afghahi, CEO, Novelics.
2: Mike Uhler, Chief Technology
Officer, MIPS Technologies.
3: Jonah Alben, Vice President of
GPU Engineering, NVIDIA.
4: Jeff Bier, Co-Founder and
President, Berkeley Design Technology.
5: Grant Martin, Chief Scientist,
Tensilica.
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Dr.
Cyrus Afghahi, CEO, Novelics.
Panelist
Cyrus Afghahi is a
semiconductor industry professional with a successful track record of
leading technology based organizations. Prior to co-founding Novelics in
2005, Dr. Afghahi was Technical Director for the Office of the CTO at
Broadcom Corporation. He has over 20 years experience leading strategic
technology initiatives in low power and high speed VLSI designs for
advanced, high performance applications. Prior to joining Broadcom, Dr.
Afghahi held key technical and management positions at Intel Corporation,
Ericson Radio and Carlsted. He received his PhD in Linkoping, Sweden in
1985. He holds more than 60 patents.
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Mike
Uhler, Chief Technology Officer, MIPS Technologies.
Panelist
Michael Uhler brings more than 25 years of engineering experience in the
semiconductor and computer industry to his role as Chief Technology Officer
at MIPS Technologies, Inc. He is responsible for driving the strategy and
vision of the MIPS Architecture, core and software products and related MIPS
standards for MIPS Technologies
Mr. Uhler has been part of the MIPS Technologies team since 1994, when he
joined the MIPS Group of Silicon Graphics, Inc. as director of engineering.
Prior to that, he spent 15 years at Digital Equipment Corporation, working
on SMP operating systems and system design, and as the lead architect for
VAX microprocessor chips. Most recently Mr. Uhler was Vice President,
Systems, Architecture, and Software Products at MIPS. Mr. Uhler holds 26
patents in computer architecture, hardware and software design, and has an
additional 11 patents pending. Mr. Uhler earned his BSEE and MSCS
degrees from the University of Arizona.
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Jonah
Alben, Vice President of GPU Engineering, NVIDIA.
Panelist
Jonah Alben has been Vice
President of GPU Engineering for NVIDIA since January 2004. Mr. Alben joined
the Company in October 1997 as an ASIC design engineer. Prior to joining,
Mr. Alben was a design engineer at Silicon Graphics. Mr. Alben holds
B.S.C.S.E. and M.S.E.E. degrees from Stanford University.
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Jeff
Bier, Co-Founder and president, Berkeley Design Technology.
Panelist
Jeff Bier is co-founder and
president of Berkeley Design Technology, Inc. (www.BDTI.com), a respected
benchmarking and consulting company focused on digital signal processing
applications. BDTI's helps technology providers build and sell winning
products, and helps system developers to reduce risk and speed time to
market.
Jeff is a recognized industry expert, frequently presenting seminars on
signal processing applications and technologies. He is also editor of BDTI’s
respected technology analysis reports, including “Buyer’s Guide to DSP
Processors,” now in its sixth edition. Jeff is also Editor in Chief and a
frequent contributor on InsideDSP.com, an online newsletter dedicated to
digital signal processing technology. Jeff earned B.S. and M.S. degrees from
Princeton University and U.C. Berkeley.
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Grant
Martin, Chief Scientist, Tensilica.
Panelist
Grant Martin is a Chief
Scientist at Tensilica, Inc. in Santa Clara, California. Before that, Grant
worked for Burroughs in Scotland for 6 years; Nortel/BNR in Canada for 10
years; and Cadence Design Systems for 9 years, eventually becoming a Cadence
Fellow in their Labs. He received his Bachelors and Masters degrees in
Mathematics (Combinatorics and Optimization) from the University of
Waterloo, Canada, in 1977 and 1978.
Grant is a co-author of ESL Design and Verification: A Prescription for
Electronic System Level Methodology, 2007, published by Morgan Kaufmann. He
is also co-author of Surviving the SOC Revolution: A Guide to Platform-Based
Design, 1999, and System Design with SystemC, 2002, and a co-editor of the
books Winning the SoC Revolution: Experiences in Real Design, and UML for
Real: Design of Embedded Real-Time Systems, June 2003, all published by
Springer (originally by Kluwer). In 2004, he co-wrote with Vladimir Nemudrov
the first book on SoC design published in Russian by Technosphera, Moscow.
Recently, he co-edited Taxonomies for the Development and Verification of
Digital Systems (Springer, 2005), and UML for SoC Design (Springer, 2005).
He has also presented many papers, talks and tutorials, and participated in
panels, at a number of major conferences. He co-chaired the VSI Alliance
Embedded Systems study group in the summer of 2001, and was co-chair of the
DAC Technical Programme Committee for Methods for 2005 and 2006. His
particular areas of interest include system-level design, IP-based design of
system-on-chip, platform-based design, and embedded software. He is a senior
member of the IEEE.
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4:30 pm -
8:30 pm
Exhibit |
Conference Exhibit & Reception Open
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8:00 -
8:15 |
Farhad
Mafie, President and CEO of Savant Company Inc.
"Welcome and Opening Remarks, Technology/Market Trends."
Farhad
has over 20
years of experience in semiconductor and computer businesses and more than 10
years of university-level teaching experience. Farhad is the former
Vice President of Marketing/Business Development and Technical Sales Engineering at
Toshiba America Electronic Components, Inc. He was responsible for marketing
the entire Toshiba standard ICs (RISC/CISC CPUs, Configurable CPUs, DSPs, Bluetooth,
Wireless ICs, RFID, MPEG-4, CCD/CMOS, Analog ICs, Automotive ICs, etc.).
He was also responsible for engineering development for Toshiba's Embedded and Digital Consumer
products & solutions based on ASSP and SoC Models.
Farhad established Toshiba's on-line
Tech-Support System as well as Toshiba's on-line System Solution Selling
methodologies for all Toshiba's products in the North American markets.
These on-line systems were adopted by Toshiba on a worldwide basis. He
also developed Toshiba's ASSP Business Unit and Technical Sales Engineering
Team as two brand new organizations for the company. Farhad has also worked at Lucent Technologies
on marketing communications ICs,
Toshiba Information Systems on product definition for Toshiba's notebooks
and handheld products, Unisys on designing new processors and computer
systems, and MSI Data on
designing data collection products. He has a Master of Science and a
Bachelor of Science degree in Electronic Engineering from California State
University, Fullerton. His combined business and academic experience
has given Farhad a unique ability to effectively communicate complex new
technologies to business professionals at all levels, as well as the ability
to foresee emerging leading-edge technologies.
Farhad is an author and a
translator, and he writes articles for a variety of journals and Web-based
magazines on technology and political affairs.
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8:15 am - 12:00 am |
Memory
sub-system Issues, Advances & Trends for
Complex
SoC Designs
Track
Chairman:
Dr.
Nader Bagherzadeh,
University of
California, Irvine. |
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Dr.
Nader Bagherzadeh,
University of
California, Irvine.
Dr. Nader
Bagherzadeh has been involved in research and development in the areas of
computer architecture, reconfigurable computing, VLSI chip design, and
computer graphics. For almost ten years ago, he was the first researcher
working on the VLSI design of a Very Long Instruction Word (VLIW) processor.
Since then, he has been working on multithreaded superscalars and their
application to signal processing and general purpose computing. His
current project at UC, Irvine is concerned with the design of coarse grain
reconfigurable pixel processors for video applications. The proposed
architecture, called MorphoSys, is versatile enough to be used for digital
signal processing tasks such as the ones encountered in wireless
communications and sonar processing. DARPA and NSF fund the MorphoSys
project (total support $1.5 million). Dr. Bagherzadeh was the Chair of
Department of Electrical and Computer Engineering in the Henry Samueli
School of Engineering at University of California, Irvine. Before
joining UC, Irvine, from 1979 to 1984, he was a member of the technical
staff (MTS) at AT&T Bell Laboratories, developing the hardware and software
components of the next-generation digital switching systems (#5 ESS).
Dr. Bagherzadeh holds a Ph.D. in computer engineering from The University of
Texas at Austin. As a Professor, he has published more than a hundred
articles in peer-reviewed journals and conference papers in areas such as
advanced computer architecture, system software techniques, and high
performance algorithms. He has trained hundreds of students who have
assumed key positions in software and computer systems design companies in
the past twelve years. He has been a Principal Investigator (PI) or
Co-PI on more than $2.5 million worth of research grants for developing
next-generation computer systems for solving computationally intensive
applications related to signal and image processing.
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8:15 - 8:45
Virage Logic |
Virage
Logic Corporation, Luigi Ternullo, Product Marketing Manager, STAR Memory
System, Virage Logic Corporation
"Achieving optimal yield in SoC designs"
The semiconductor industry has evolved to the point of a true competitive
environment, where time-to-market and cost competitiveness are the two major
factors that determine if a product is successful in the market place. Cost
competitiveness is mainly driven by die size and ultimately yield. Die size
and yield optimization are not new requirements to the semiconductor
industry, but how these requirements have been addressed as compared to
proposals for addressing future needs may slightly differ. Embedded
memory IP can be a large component in the yield equation associated with SoC
designs. Embedded memories in a SoC design can also be a facilitator to
improving yield. State of the art design techniques as well as the
intelligent use of redundancy are required to ensure high yielding memories.
However, more often than not, issues arise in silicon and manifest
themselves in embedded memories. Having the ability to quickly and easily
locate the source of the silicon issue can be paramount to realizing
aggressive yield targets. To enable quick and easy identification of silicon
issues that typically manifest themselves in the embedded memory, designers
must plan to incorporate an embedded memory test solution that can also be
controlled through a tester to quickly and easily identify potential silicon
issues.
Bio: Luigi Ternullo serves as Product Marketing Manager of Virage
Logic’s STAR Memory System™ for embedded, on-chip test and repair of
multi-megabit memories. Prior to joining Virage Logic in 2006, Ternullo held
technical marketing management positions and senior engineering management
positions at Agere, Vanguard International Semiconductor, and IBM. His range
of experience includes SRAM design, memory and logic built-in self-test
(MBIST and LBIST). Mr. Ternullo also holds over 25 patents in BIST and
memory design, and has authored several BIST papers. He holds a B.S. and
M.S. in Electrical Engineering from Rochester Institute of Technology, and
M.B.A. from Lehigh University.
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8:45 - 9:15
Micron |
Jim
Cooke, Director of Application Engineering, Micron Technologies.
"On-Chip or Off-Chip Trends?"
One of the most important questions designers are asking today is whether
to integrate Flash technology on-chip or move it off-chip. In this
presentation, we will discuss the growing acceptance of off-chip NAND
Flash technology in embedded applications such as set-top boxes, MP3
players, digital cameras, and new smart cell phones. In the process, we
will cover trends, reliability challenges, and advanced new features and
security enhancements in NAND technology. We will also explore new
possibilities in performance and power trade-offs in the smaller
geometries as we move toward mass production on 90nm—and in the near
future on 65nm. And finally, we will present packaging trends that present
a feasible and promising option to integrating on-chip memory.
Jim Cooke is a Director of Application Engineering for Micron’s Mobile Memory
Group. Prior to joining Micron, he managed the applications engineering
group and hardware engineering team for Toshiba America Electronic
Components. Mr. Cooke has over 20 years of hands-on systems-level design
experience in embedded applications and digital consumer markets. He holds
a BSEE from the University of Massachusetts.
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9:15 - 9:45
Rambus |
Dr.
Tom Sheffler, Senior Principal Engineer.
"Managing Complexity in a PHY Verification Flow"
Leading-edge memory interface PHY design requires custom flows built with
a variety of tools that use a multiplicity of design representations. A
verification team supporting geographically distributed teams, each with
multiple tools and multiple representations can be confronted with
overwhelming complexity if the
necessary number of model variations and combinations is not planned for
and managed in a rigorous manner. This talk describes our experiences
developing a means to manage necessary design variations and models, and
the correlations between them. In the process of designing a
database-driven configuration-based flow, we provided enhanced flexibility
while increasing stability and reproducibility. We describe our goals, our
organization and how we would like verification tools to support enhanced
design configuration in the future.
Tom Sheffler is a Senior Principal Engineer at Rambus. He joined Rambus
twelve years ago and has served in the verification and architecture
groups. Tom received his PhD and MS in Computer Engineering from Carnegie
Mellon, and his BSEE from the University of Virginia. He holds four
patents. At Rambus, Tom was a lead in the verification of the logical
architecture of the Direct RDRAM as well as the XDR DRAM and PHY
interface. Tom has addressed the issues of how to accurately capture the
behavior of Rambus mixed-signal designs in means that are useful as
communication tools between people and software. Previous to joining
Rambus, Tom worked on compilers and runtime systems for parallel
supercomputers while at the Research Institute for Advanced Computer
Science at NASA Ames. |
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9:45 - 10:00
Morning Break
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Morning Break |
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10:00 -
10:30
National Semiconductor
Keynote |
Dr.
Ahmad Bahai, National Fellow and Chief Technology Officer, NS Labs, National
Semiconductor. Adjunct Professor, Stanford University, UC Berkeley.
Keynote
Bio: Dr. Bahai is
recognized throughout the industry and academia as a leading expert on
wireless systems. He joined National in January 2000 as part of the
acquisition of Algorex, a company he co-founded. Since becoming a part of
the company, Dr. Bahai and his team in Fremont, CA have developed a novel
WCDMA architecture and brought it to prototype stage. Prior to founding
Algorex, he was a technical manager for the Wireless Communications Group of
AT&T Bell Laboratories and a staff scientist for Teknekron Communications.
Dr. Bahai is a consulting professor for the Electrical Engineering
Department of Stanford University and a visiting professor at UC Berkeley.
He is the author of over 30 technical papers and reports and holds five key
patents in the Communications and Signal Processing field. Since 1998, Dr.
Bahai has been an editor of IEEE Communication Letters and keynote speaker
for many key technical conferences and seminars. Several of his papers were
awarded Best Invited Papers/Best Keynotes. In 1999 he published the first
textbook in OFDM, "Multi-Carrier Digital Communications, Theory &
Applications of OFDM," which is widely used in academia and industry. Dr.
Bahai has an MSEE degree from the University of London, Imperial College and
a PhD EE from the University of California at Berkeley. |
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10:30 - 11:00
Innovative Silicon |
Jeff Mitchell, Director of
Technical Marketing, Innovative Silicon.
"Memory for the New Millennium
– Keeping Moor’s Law Alive."
Continuing to scale along Moore’s Law to smaller die sizes and lower cost is
essential to the future growth and continued success of the semiconductor
industry. Ever-smaller geometries are making it difficult to shrink not just
logic transistors but embedded memory structures as well. Memory consumes
the largest portion of the die area of many SoC designs, and with increased
leakage current affecting embedded SRAM and capacitor formation becoming
progressively more difficult at every embedded DRAM generation, a new
technology breakthrough is needed in order to eliminate the risk of SOCs
becoming memory limited. This presentation will discuss how a true,
single-transistor memory technology is once again getting memory scaling
back onto the Moore’s Law curve. This new type of memory is being designed
into embedded applications as well as being adopted by the standalone DRAM
industry. With the potential for the speed of embedded SRAM and the density
of embedded DRAM, there is now a new solution to many of the functionality
and cost challenges facing SoC designers today.
Bio: Jeff Mitchell is Director of Technical Marketing at
Innovative Silicon. He has more than 20 years of experience in the
electronics industry and has been awarded several patents. He has had a
varied career, holding positions in engineering, marketing, and business
development. Mitchell has a B.S. in Engineering from Harvey Mudd College.
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11:00 - 11:30
Kilopass Technology |
Craig Rawlings, Director of
Marketing, Kilopass Technology Inc.
"Embedded
Non-Volatile Memory (NVM)."
As mask costs skyrocket for SOC designs on advanced process geometries,
designers are highly motivated to develop new approaches for reducing
multiple chipsets into a single SOC platform solution. Such a Platform SOC
must support multiple product feature sets, interface variations, and
individual feature functionality that are all configurable in
post-production. SOC application-specific functionality can be configured
through programmable firmware, firmware parameters, and configurable
hardware, utilizing embedded non-volatile memory (NVM).
Bio: Craig Rawlings has more than 15 years of experience in the
semiconductor industry. Prior to joining Kilopass, Craig held management and
executive-level positions at Hewlett-Packard, Actel, Resilience, and
Progress Software. Kilopass is Craig's fourth early stage start-up
experience. Craig's first start-up right out of engineering school was
Cericor which was later purchased by HP. He was also part of the initial
team at Actel and led that company's business expansion in the US, Japan,
and Asia Pacific participating in Actel's subsequent IPO. Craig holds a
B.S.E.E. degree and a Masters of Business Administration from Brigham Young
University.
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11:30 - 12:00
Novelics |
Dr.
Gil Winograd, Chief Operating Officer & Co-Founder, Novelics Corporation.
"Innovative Embedded Memories."
Bio: Prior to
co-founding Novelics, Gil Winograd was a Principal Scientist at Broadcom
Corporation responsible for the design of leading-edge memories, high speed
full-custom circuits, and compiler and software automation processes for
custom circuits. Dr. Winograd brings to Novelics a diverse background of
software design, IC design, and device physics and fabrication. Dr. Winograd
received his BSEE from the University of Illinois, Champaign in 1991, his
MSEE from the University of Illinois in 1994 in Computer Engineering, and
his Ph.D. from Stanford University in 2000, specializing in lithography. He
has six technical publications and more than 30 patents issued or pending.
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12:00 - 1:00
Lunch |
Multicore,
CPUs, DSPs & NoCs for Complex SoCs
Track
Chairman: Farhad Mafie, Savant Company Inc. |
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1:00 - 2:00
Panel
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Panel:
“Emerging
Wireless Chips: The Development & Integration Challenges”
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Inside GNSS
Trimble
Broadcom
SiRF
Technology
Qualcomm
Freescale
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Glen
Gibbons, Inside GNSS, Editor and Managing Partner.
Moderator
Glen Gibbons, the editor and
managing partner, has spent eighteen years covering and commenting on GNSS
news and developments. He was the founding editor of GPS World, Galileo’s
World, and GPS World Newsletter. He and partner Eliza Schmidkunz launched
Inside GNSS in January 2006.
Panelists
1:
Bruce Peetz,
Vice President of Advanced Technologies, Trimble.
2:
Charles Abraham, Director of Engineering for the GPS
Business Unit of Broadcom, Corporation.
3:
Sanjai Kohli, Chief Technical Officer,
SiRF
Technology.
4:
Dr.
Cormac Conroy, VP Engineering,
Qualcomm
5:
Clint Powell, Chief Architect and Global Platform Systems and Architecture
Manager, WCO, Freescale.
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Bruce Peetz,
Vice President of Advanced Technologies, Trimble.
Panelist
Bruce Peetz has been with
Trimble Navigation Limited for nearly 20 years in a variety of engineering
and management positions, and is currently serving as the Vice President of
Advanced Technology and Systems. Prior to Trimble he was with
Hewlett-Packard and Hughes Aircraft Company. A graduate of MIT, Mr. Peetz
spent much of his career in businesses that depend on combining different
technologies, particularly in integrating mixed signal systems, most
recently dealing with GPS, optical, and laser positioning systems integrated
with communication.
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Charles
Abraham, Director of Engineering for the GPS Business Unit of Broadcom,
Corporation.
Panelist
Charles Abraham is Director
of Engineering for the GPS Business Unit of Broadcom, Corporation. He was
previously co-founder and Executive Vice-President of Engineering at Global
Locate, which was acquired by Broadcom in July 2007. He is a pioneer in the
fields of assisted GPS and high sensitivity receiver architecture and holds
dozens of issued patents in the field. Mr. Abraham was a Vice President at
Magellan Corporation where he focused on the development of precision
surveying systems. Previously he was with Trimble Navigation, where he
contributed to the design of low cost GPS chipsets. Before entering the GPS
field, Mr. Abraham worked in the field of satellite communications at Hughes
Aircraft. He holds an MSEE from the University of Southern California and a
BSEE from the University of California at San Diego.
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Sanjai
Kohli, Chief Technical Officer,
SiRF
Technology.
Panelist
Sanjai Kohli is the chief
technology officer (CTO) of SiRF Technology Inc. Previously he was the
founder and CTO of Truespan, which developed semiconductors for mobile video
applications. Previously he was a cofounder, president, and CEO of
WirelessHome (WH), which developed a point to multipoint system. WH was
acquired by Proxim/Western Multiplex in 2001. At Proxim he was the
vice-president/general manager for the Multipoint Systems Division,
responsible for the Tsunami and Quick bridge product lines. Prior to WH,
Kohli was the cofounder, president, and vice-president of engineering of
SiRF Technology. At SiRF he was responsible for the development of the first
two generations of GPS chipsets and software, including Sirfstar II. Prior
to SiRF, he founded Software Technology & Systems (STS) that developed smart
munitions and spread spectrum technology, serving as its president and CEO.
Kohli holds a B.S. in engineering from the Indian Institute of
Technology–Bombay and an M.S. in system science from Washington University,
St. Louis, Missouri, USA. He has more than 20 published papers and 20 issued
patents.
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Dr.
Cormac Conroy, VP Engineering,
Qualcomm.
Panelist
Dr. Cormac S. G. Conroy
received the Ph.D. in Electrical Engineering from the University of
California, Berkeley in 1994 for work on high-speed A/D conversion in CMOS.
After graduating, he was at IBM Storage Systems Division in San Jose, and in
August 1994 joined DataPath Systems where he worked on highly integrated
mixed-signal ICs for storage and communications. At DataPath, he led the
design and development efforts in CMOS ADSL analog front end ICs over
multiple product generations. DataPath was acquired by LSI Logic in May
2000.
In early 2001, with Dr. Beomsup Kim, he co-founded Berkäna Wireless Inc., a
Silicon Valley-based fabless semiconductor company developing highly
integrated CMOS RF solutions for cellular phone applications. Berkana was
acquired by Qualcomm in 2006. Since January 2006, he has been VP Engineering
at the Qualcomm Silicon Valley organization and is responsible for wireless
connectivity chipset solutions including GPS and navigation.
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Clint
Powell, Chief Architect and Global Platform Systems and Architecture
Manager, WCO, Freescale.
Panelist
Clint Powell is responsible
for defining the next generation System on a Chip (SoC), System in a Package
(SiP) and Platform in a Package (PiP) architectures and setting the
technical strategy for the Wireless Connectivity Operations at Freescale. By
combining novel SoC and Radio Transceiver Architectures with State of the
Art Process Technology and Packaging Concepts, he has established leading
edge SiP and PiP products for the wireless connectivity space. Previous to
this, Clint was the WPAN Chief Architect and a Distinguished Member of
Technical Staff.
Prior to Freescale, Clint was with Motorola for 15 years and was a Member of
the Technical Staff and a Science Advisory Board Associate. He held various
roles in Applied Research, Advanced Technology, Wireless Systems Integration
and the Semiconductor Products Sector where he led the architectural
definition of communications and video systems. Prior to that, he led the
development of digital and analog signal processing communications systems
for digital and mixed-signal subsystems. In addition, he defined a system
definition and modeling to implementation flow that is used today.
Clint is the author of several papers in the area of wireless communications
and holds 29 U.S. Patents. He currently serves as the Chair of the IEEE
802.15 4c Task Group (TG4C) to define an 802.15.4 Standard that meets the
Chinese Regulatory Requirements for the 700 MHz band. He also serves as the
Secretary of the ZigBee Qualification Group (ZQG) in the ZigBee Alliance.
Previously he served on the IEEE 802.15.4b (IEEE 802.15.4 2006) standards
committee as the PHY Editor and as the Vice Chair of the Application
Framework Group (AFG) in the ZigBee Alliance.
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2:00 - 2:30
Carnegie Mellon University
Keynote |
Dr. Rob
Rutenbar, Professor of Electrical & Computer Engineering, Director of the
National FCRP Focus Center for Circuit & System Solutions. Carnegie Mellon
University
Keynote:
"From Wall Street to
Silicon Valley: Using the Mathematics of Money and Risk for Fast Statistical
IC Design"
Moore's law device scaling dramatically increases the statistical
variability with which tomorrow’s chips must contend. Devices with atomic
dimensions don't have deterministic parameters: every behavior we want to
model is a messy smear of probability. How should we attack such problems?
Is slow, expensive Monte Carlo analysis our only option? Is the silicon
community unique in facing such problems? As it turns out, problems in
computational finance and risk analysis share many of the characteristics
that challenge us in statistical circuit analysis: high dimensionality,
profound nonlinearity, stringent accuracy requirements, and expensive
analysis (i.e., circuit simulation). In this talk I'll show examples of
adapting computational ideas from Wall Street for use in the silicon world.
I'll show how the same methods used to price complex securities can be
adapted to compute silicon yields, giving speedups of 2x - 50x. I'll show
how methods used to analyze the statistics of rare events (like the size of
the biggest wave in a hurricane like Katrina) can be used to analyze
failures in SRAM, giving speedups of 20,000x. Some of our best engineering
students have found careers on Wall Street in recent years. Work such as
this suggests that this "brain drain" need not be such a one-way thing.
BIO: Rob A. Rutenbar received the Ph.D. from the University of
Michigan in 1984, and then joined the faculty at Carnegie Mellon University.
He currently holds the Stephen Jatras Chair in Electrical and Computer
Engineering. He has worked on tools for custom circuit synthesis and
optimization for over 20 years. In 1998 he co-founded Neolinear Inc. to
commercialize the first practical synthesis tools for analog designs. He
served as Neolinear's Chief Scientist until its acquisition by Cadence in
2004. He is the founding Director of the US national Focus Research Center
for Circuits and System Solutions -- called "C2S2". C2S2 is a CMU-led
consortium of 17 US universities and over 50 faculty funded by the US
semiconductor industry and US government to address future circuit
challenges. He has won many awards over his career, including the 2001
Semiconductor Research Corporation Aristotle Award for excellence in
education, and most recently, the 2007 IEEE Circuits & Systems Industrial
Pioneer Award. His work has been featured in venues ranging from "EE Times"
to "The Economist" magazine. He is a Fellow of the IEEE.
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Innovative Tools & Solutions: For Complex SoC Designs
Track
Chairman: Dr. Jim Lipman, Vice President, Cain Communications |
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Dr.
Jim Lipman, Vice President, Cain Communications
Track
Chairman: Dr. Jim Lipman
Jim Lipman is currently Vice
President of Client Services at Cain Communications, an agency providing
marketing communications services to semiconductor, IP, EDA and other
high-tech companies of all sizes. His prior work experience includes
editorial positions at EDN and TechOnLine, the latter where he was Content
Director; marketing and training positions at VLSI Technology; and various
engineering jobs at Hewlett-Packard and Texas Instruments. Jim has an
Electrical Engineering Doctorate from SMU and an MBA from Golden Gate
University.
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2:30 - 3:00
Synopsys |
Navraj Nandra, Director of
Product Marketing for the Mixed-Signal Products,
Synopsys.
"Embedding Multi-Gb/s Serial Interconnects into 65 nm and 45 nm SoC’s."
High speed serial interconnects such as PCI Express 2.0 and 10 Gigabit
Ethernet are becoming available as IP (Intellectual Property). And these
blocks and are being integrated into 65 nm and 45 nm CMOS SoC’s and FPGA's.
The multi-gigabit per second speed, complexity of the protocol, influence of
the channel and variations in the deep sub-micron technology is resulting in
new design challenges not only for the IP developer but also for the SoC
integrator – in this case the consumer of the IP. Although equally skilled
in design there are differences in the IP development and SoC integration
tasks. The IP development team must ensure that they deliver all the
necessary views for successful integration, without knowing in detail the
SoC environment, and in most cases this involves thorough validation of
functionality in the target foundry through test-chips. The SoC team must be
able to integrate the IP and perform all the necessary chip-level
verification. This is causing designers to re-think the verification and
validation tasks of the IP. For example, pre-layout verification in terms of
device mis-match and Monte Carlo simulations is becoming a poorer predictor
of performance, increasing the importance of understanding the impact
systematic variations based on physical changes to the device thereby
necessitating detailed post-layout parasitic extracted simulations. Silicon
test-chips where visibility into the link performance, supply/substrate
noise rejection and ESD are the most important tasks required for
validation. The necessary tasks of both the IP developer and integrator to
ensure a fully functional SoC will be presented.
Bio: Navraj Nandra joined Synopsys in February 2005 as Director of
Product Marketing for the mixed-signal products that include SERDES, USB and
DDR2. He has worked in the semiconductor industry since the mid 80's as an
analog/mixed signal IC designer for Philips Semiconductors,
austriamicrosystems, (San Jose & Austria) and EM-Marin (Switzerland). He has
been responsible for the complete design of a number of analog front ends in
application areas such as digital audio, RFID and automotive. He joined
Synopsys from Barcelona Design where he was Director of Application
Engineering. During his four years at Barcelona he was responsible for pre-
and post-sales support for Barcelona's analog synthesis technology. Navraj
holds a masters degree in Microelectronics, majoring in analog IC design,
from Brunel University and a post-graduate diploma in Process Technology
from Middlesex University. He has presented at numerous technical
conferences on mixed-signal design, analog IP and analog synthesis/EDA. He
has been awarded patents in RFID design.
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3:00 - 3:30
Cadence Design Systems |
Steve
Carlson, Cadence Design Systems.
"Economic Impact of Low-Power Design."
As a broader set of products
begin have power dissipation move to center stage as a primary design
criteria, the costs associated with the first time deployment of advanced
low power design techniques need to be anticipated, measured, and managed.
The costs come in the form of methodology and tool education, re-tooling of
the design environment, and the efficiency of the solution adopted. The
latter issue, design efficiency, can be the single biggest contributor to
"cost", which manifests itself in the forms of partial realization of power
savings, schedule slips, and design failures.
Bio: Steve is
a Vice President on the Cadence Synthesis team. In that role he is focused
on marketing the solution for the best Quality-of-Silicon (chip speed, area,
power, test measured after wires). Carlson reports to Chi-Ping Hsu,
Corporate VP for New Synthesis at Cadence. Steve joined Cadence in
April in 2003 via the Get2Chip acquisition, where he was the VP of
Marketing. Prior to Get2Chip, Steve was the CEO of Tharas Systems, a
hardware acceleration company. Steve has also held various management
positions at Escalade, LSI Logic, United Technologies and Synopsys. At
Synopsys, Steve was a part of the original Design Compiler technical team
responsible for timing analysis and optimization. Steve was the author
of the industry’s first book on high-level design: Introduction to
HDL-based Design Using VHDL. Steve has a BSEE, a BSCS, and an
MSEE, all from the University of Colorado. |
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3:30 - 3:45
Afternoon
Break |
Afternoon Break |
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The SPIRIT Consortium
(Mentor Graphics) |
Bill
Chown, Product Group Director for the System-Level Engineering Division at
Mentor Graphics, Representing The SPIRIT Consortium.
"Design
Flow integration with IP-XACT"
The IP-XACT specifications
provide machine-readable descriptions of IP to enable automated IP and SoC
configuration, integration and verification in multi-vendor design flows.
IP-XACT standardizes a meta-data format for IP description and assembly, in
use to complete some of the industry's leading SoC devices. The applications
of IP-XACT encompass the use of automated tools, generators and IP
integration for synthesis, verification, documentation and other
implementation flows, and span design configuration and integration
requirements for RTL, ESL and advanced verification methodologies.
Bio: Bill Chown, currently a product group director for the
system-level engineering division at Mentor Graphics, moved to the
semiconductor industry with Intersil Semiconductors, where he went from
designing mixed signal and DSP systems, at chip and board level in the UK,
to managing projects through to layout and production test. He subsequently
worked in EDA and test software development in Europe and the US with Mentor
Graphics, Summit Design/TSSI, Integrated Measurement Systems and Credence. A
twenty-five year veteran, Bill currently specializes in TLM and RTL
platform-based design and verification. He has been involved with standards
activities for several years, serving in the CFI, ECSI, and STIL
initiatives, is past chair of the TTTC TAC on Virtual Test, is currently a
member of the STIL working group, and is a board member for The SPIRIT
Consortium and of OMG. Bill earned an Electronic Engineering degree from the
University of Wales and an MBA from the University of Oregon. |
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3:45 - 4:15
Actel |
Mike Thompson,
Senior Engineering
Manager, Actel Corporation.
"Portable Product Design
with Cortex-M1 in Low-power FPGAs."
The increasing demand for portable products is forcing designers to look for
ways to make applications run longer from finite battery resources. This is
happening against the backdrop of shrink induced limitations to
semiconductor physics resulting in increased leakage and changes to the
traditional methods of controlling power consumption. At the same time
products are becoming more complex with designers adding more features while
dealing with rapidly changing markets and shortened design cycles driving
the need for increased flexibility in the system platforms that they are
using. By implementing battery powered applications with Flash FPGAs that
offer sophisticated low power operating modes, designers can take advantage
of the flexibility of programmable logic while developing products that
maximize battery life. And, coupled with new state-of-the-art embedded soft
processors like ARM’s Cortex-M1 they can meet the increasing demand for
performance while maximizing power efficiency. This presentation will look
at the implementation of portable applications taking advantage of the
capabilities offered by low power Flash FPGAs and the Cortex-M1 processor.
Bio: Mike Thompson is Senior Manager, IP & Applications Solution
Marketing at Actel Corp. where he is responsible for the development and
infrastructure support of new microprocessor IP cores for use in the
company’s FPGAs. He has more than 25 years of experience in both design and
support of IP, microprocessors, microcontrollers and the development of
embedded applications. He holds a BSEE from Northern Illinois University and
an MBA from Santa Clara University. He is currently managing the release of
Actel’s optimized version of the ARM Cortex-M1 – the first ARM processor
design specifically for implementation in FPGAs.
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4:15 - 5:45
Panel |
Panel:
“Structured ASICs: Dead or Alive”
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EDN
Toshiba
eASIC
InSilica
Altera
Kenet
Faraday |
Steve Leibson, Contributing Editor, EDN
Moderator
Bio: Steve Leibson is an experienced hardware and software design
engineer, engineering manager, and design consultant. He spent 10 years
working at electronic systems companies including HP’s Desktop Computer
Division, Auto-Trol Technology (graphics workstations), and Cadnetix (EDA
workstations) after earning his BSEE cum laude from Case Western Reserve
University. At HP, Auto-Trol, and Cadnetix, he specialized in the design of
desktop computers and workstations, especially in the areas of system and
I/O design. He then spent 15 years as an award-winning technology
journalist, publishing more than 200 articles in Microprocessor Report, EDN,
EE Times, Electronic News, and the Embedded Developers Journal. He served as
Editor in Chief of both EDN and the Microprocessor Report and was the
founding Editor in Chief of the Embedded Developers Journal. Leibson has
just written and published “Designing SOCs with Configured Cores,” a
treatise on 21st-century MPSOC design. Twenty years earlier, he wrote and
published “The Handbook of Microcomputer Interfacing,” which was published
in English, French, and Dutch, and was used as a university textbook for
many years. In 2004, he co-authored “Engineering the Complex SOC” with
Tensilica’s president and CEO Chris Rowen, which has also been used as a
textbook in university classes. He has also contributed chapters to several
other SOC design books since joining Tensilica in 2001.
Panelists:
1:
Soheila Lighvani, Director, Design Engineering, Western Area Design Center,
Toshiba America Electronic Components.
2:
Jasbinder Bhoot, Senior Director, Marketing, eASIC Corporation.
3: Sunil Baliga, VP & GM, Custom Silicon Business, InSilica.
4: Paul Hollingworth, Senior Director of the HardCopy Product Group,
Altera.
5: Phillip LoPresti, CEO & President, Kenet Inc.
6: Chris Moezzi, Vice President of Business Development, Faraday
Technology.
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Soheila
Lighvani, Director, Design Engineering, Toshiba, Western Area Design Center.
Panelist
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Paul
Hollingworth, Senior Director, HardCopy Product Group, Altera Corporation.
Panelist
Paul Hollingworth is the Senior Director of the HardCopy Product Group at
Altera. Mr. Hollingworth joined Altera in 1996 as the European Marketing
Manager, where he ran the product, corporate and commercial marketing
activities for Altera in Europe. Prior to that, Mr. Hollingworth spent 11
years in the ASIC industry, working for LSI Logic in England and Germany in
a range of technical and marketing roles, and at Thesys where he was
responsible for the Communications Products Group. Mr. Hollingworth received
a BSEE in physics and electronics and a Masters in microelectronics from
Durham University in England.
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Sunil Baliga, VP & GM, Custom Silicon Business, InSilica.
Panelist
Sunil Baliga currently is the
VP & GM of the custom silicon business unit at inSilica Inc. a low-power
ASIC supplier focused on 90nm and 65nm designs. He has more than 15 years of
experience in marketing semiconductors, primarily in the programmable logic
and ASIC markets. Sunil has a B.S. Electrical Engineering and Computer
Science from the University of Colorado, Boulder and a M.B.A. from
Georgetown University. He also has studied International Business at Oxford
University.
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Jasbinder
Bhoot, Senior Director of Marketing, eASIC Corporation.
Panelist
Jasbinder Bhoot is Senior
Director of Marketing at eASIC Corporation. He is responsible for setting
the marketing strategy for the company and has overall responsibility for
product definition and deployment. Mr. Bhoot has more than 15 years of ASIC
and FPGA experience. Prior to joining eASIC, he was part of the vertical
marketing team at Xilinx. In this role, he managed the partner solutions
team that included IP, design services, EDA, and ASSPs. Mr. Bhoot has also
held technical and business management positions at LSI Logic, Altera, Sony
Semiconductor, and Texas Instruments. Mr. Bhoot holds a B.S. in electronic
engineering from the University of Westminster and an M.B.A. from the
University of Nottingham.
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Phillip LoPresti, CEO & President, Kenet Inc.
Panelist
Phillip LoPresti, Chief
Executive Officer & President. Prior to joining Kenet in 2006, Mr. LoPresti
was associate vice president and general manager of the Custom LSI Solutions
strategic business unit at NEC Electronics America, where he successfully
expanded the company’s ASIC technology business in North America. Mr.
LoPresti joined NEC in 1984 as an engineer in the company’s design center
and later was promoted to manager. Subsequently he was general manager and
then business operations manager of the system LSI organization, where he
oversaw all system LSI products and sales. Earlier in his career, Mr.
LoPresti was employed by RCA Automated Systems and also was an adjunct
professor of electronics at Northeastern University in Boston,
Massachusetts. He holds bachelor’s and master’s of science degrees in
electrical
engineering from Boston University.
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Chris
Moezzi, Vice President of Business Development, Faraday Technology.
Panelist
Christopher Moezzi has 18
years of experience in product management, marketing, and R&D of
semiconductor and communication systems. He is responsible for the business
development, product planning and marketing of Faraday’s Platform ASICs. Mr.
Moezzi was Sr. Director of strategic marketing at GlobespanVirata (Acquired
by Connexant) before joining Faraday in 2004. He also held marketing and
engineering positions at T-sqware, and Alcatel-Lucent. Moezzi holds an
M.B.A. from Northeastern University (Boston, MA) and an M.S.E.E from
Southern Methodist University (Dallas, TX).
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5:45 – 6:00
Savant |
5th International SoC Conference Closing
Remarks. Farhad Mafie, President & CEO. |
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Company Inc. International
SoC Conference and Exhibit said they would recommend this SoC Conference to
someone else!
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